| /dports/lang/sdcc/sdcc-4.0.0/sim/ucsim/z80.src/ |
| H A D | r2kcl.h | 38 #define SADR 0xC0 /* Serial A Data Register in IOI (internal I/O space) */ macro
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/i2c/bench/verilog/ |
| H A D | tst_bench_top.v | 108 parameter SADR = 7'b0010_000; constant
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| /dports/devel/libmba/libmba-0.9.1/src/ |
| H A D | suba.c | 48 #define SADR(s,r) (void *)((char *)(s) + (r)) macro
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/sound/soc/pxa/ |
| H A D | pxa2xx-i2s.c | 38 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ macro
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| /dports/multimedia/libv4l/linux-5.13-rc2/sound/soc/pxa/ |
| H A D | pxa2xx-i2s.c | 38 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ macro
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| /dports/devel/openwince-include/include-0.4.2/arm/pxa2x0/ |
| H A D | i2s.h | 89 #define SADR I2S_pointer->sadr macro
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/sound/soc/pxa/ |
| H A D | pxa2xx-i2s.c | 38 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ macro
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| /dports/emulators/z80pack/z80pack-1.37/imsaisim/ |
| H A D | basic4k.asm | 2543 SADR INC HL ;POINT NEXT BYTE label
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| H A D | basic8k.asm | 4693 SADR: INX H ;POINT NEXT BYTE label
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| /dports/emulators/qemu/qemu-6.2.0/hw/arm/ |
| H A D | pxa2xx.c | 1624 #define SADR 0x80 /* Serial Audio Data register */ macro
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| /dports/emulators/qemu42/qemu-4.2.1/hw/arm/ |
| H A D | pxa2xx.c | 1598 #define SADR 0x80 /* Serial Audio Data register */ macro
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| /dports/emulators/qemu60/qemu-6.0.0/hw/arm/ |
| H A D | pxa2xx.c | 1624 #define SADR 0x80 /* Serial Audio Data register */ macro
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| /dports/emulators/qemu-utils/qemu-4.2.1/hw/arm/ |
| H A D | pxa2xx.c | 1598 #define SADR 0x80 /* Serial Audio Data register */ macro
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/arm/ |
| H A D | pxa2xx.c | 1594 #define SADR 0x80 /* Serial Audio Data register */ macro
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| /dports/emulators/qemu5/qemu-5.2.0/hw/arm/ |
| H A D | pxa2xx.c | 1623 #define SADR 0x80 /* Serial Audio Data register */ macro
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/arm/ |
| H A D | pxa2xx.c | 1624 #define SADR 0x80 /* Serial Audio Data register */ macro
|
| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/arm/ |
| H A D | pxa2xx.c | 1603 #define SADR 0x80 /* Serial Audio Data register */ macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/arm/ |
| H A D | pxa2xx.c | 1603 #define SADR 0x80 /* Serial Audio Data register */ macro
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| /dports/devel/codeblocks/codeblocks-20.03/src/plugins/scriptedwizard/resources/arm/files/phyCORE-PXA255/h/ |
| H A D | pxa255regs.h | 405 #define SADR __REG(I2S_BASE+0x0080) /* Serial Audio Data Register (TX and RX FIFO access Register… macro
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 359 #define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 359 #define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 359 #define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ macro
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 359 #define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ macro
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 359 #define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ macro
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| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-pxa/ |
| H A D | pxa-regs.h | 359 #define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ macro
|