1 2-- Copyright (C) 2001 Bill Billowitch. 3 4-- Some of the work to develop this test suite was done with Air Force 5-- support. The Air Force and Bill Billowitch assume no 6-- responsibilities for this software. 7 8-- This file is part of VESTs (Vhdl tESTs). 9 10-- VESTs is free software; you can redistribute it and/or modify it 11-- under the terms of the GNU General Public License as published by the 12-- Free Software Foundation; either version 2 of the License, or (at 13-- your option) any later version. 14 15-- VESTs is distributed in the hope that it will be useful, but WITHOUT 16-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18-- for more details. 19 20-- You should have received a copy of the GNU General Public License 21-- along with VESTs; if not, write to the Free Software Foundation, 22-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 24-- --------------------------------------------------------------------- 25-- 26-- $Id: tc878.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ 27-- $Revision: 1.2 $ 28-- 29-- --------------------------------------------------------------------- 30 31package c10s01b00x00p03n01i00878pkg is 32 constant UNIT_DELAY: TIME := 1 ns; 33end c10s01b00x00p03n01i00878pkg; 34 35-- a nand gate 36entity ENT1 is 37 port ( BITIN1, BITIN2 : in BIT; 38 BITOUT: out BIT ); 39end ENT1; 40 41use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY; 42architecture ARC1 of ENT1 is 43begin 44 BITOUT <= ( BITIN1 nand BITIN2 ) after UNIT_DELAY; 45end ARC1; 46 47configuration CON1 of ENT1 is 48 for ARC1 49 end for; 50end CON1; 51 52-- build an inverter from nand-nand logic 53entity ENT2 is 54 port ( GOING_IN: in BIT; 55 COMING_OUT: out BIT ); 56end ENT2; 57 58architecture ARC2 of ENT2 is 59 component NAND_BOX 60 port ( IN1, IN2: in BIT; OUT1: out BIT ); 61 end component; 62 signal STUCKAT_HIGH: BIT := '1'; 63begin 64 NAND_COMP: NAND_BOX port map ( GOING_IN, STUCKAT_HIGH, COMING_OUT ); 65end ARC2; 66 67use WORK.CON1; 68configuration CON2 of ENT2 is 69 for ARC2 70 for NAND_COMP: NAND_BOX 71 use configuration CON1 72 port map ( IN1, IN2, OUT1 ); 73 end for; 74 end for; 75end CON2; 76 77-- declare a test bench 78ENTITY c10s01b00x00p03n01i00878ent IS 79END c10s01b00x00p03n01i00878ent; 80 81use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY; 82ARCHITECTURE c10s01b00x00p03n01i00878arch OF c10s01b00x00p03n01i00878ent IS 83 component INV 84 port ( ENTRA: in BIT; SALE: out BIT ); 85 end component; 86 signal SIGIN, SIGOUT: BIT; 87BEGIN 88 INVERTER: INV port map ( SIGIN, SIGOUT ); 89 TESTING: PROCESS 90 variable k : integer := 0; 91 BEGIN 92 SIGIN <= '0'; 93 wait for ( 2 * UNIT_DELAY ); 94 if (SIGOUT /= '1') then 95 k := 1; 96 end if; 97 assert ( SIGOUT = '1' ) 98 report "didn't invert low to high" severity FAILURE; 99 wait for ( 3 * UNIT_DELAY ); 100 SIGIN <= '1'; 101 wait for ( 2 * UNIT_DELAY ); 102 if (SIGOUT /= '0') then 103 k := 1; 104 end if; 105 assert ( SIGOUT = '0' ) 106 report "didn't invert high to low" severity FAILURE; 107 assert NOT( k=0 ) 108 report "***PASSED TEST: c10s01b00x00p03n01i00878" 109 severity NOTE; 110 assert ( k=0 ) 111 report "***FAILED TEST: c10s01b00x00p03n01i00878 - A declartive region is formed by the text of a configuration declaration." 112 severity ERROR; 113 wait; 114 END PROCESS TESTING; 115 116END c10s01b00x00p03n01i00878arch; 117 118use WORK.CON2; 119configuration c10s01b00x00p03n01i00878cfg of c10s01b00x00p03n01i00878ent is 120 for c10s01b00x00p03n01i00878arch 121 for INVERTER: INV 122 use configuration CON2 123 port map ( ENTRA, SALE ); 124 end for; 125 end for; 126end c10s01b00x00p03n01i00878cfg; 127