| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/zpu/ |
| H A D | zpu_top_pkg.vhd | 14 areset : in std_logic; port in zpu_top_pkg.zpu_wb_bridge
32 port ( areset : in std_logic; port in zpu_top_pkg.zpu_system
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/zpu/ |
| H A D | zpu_top_pkg.vhd | 14 areset : in std_logic; port in zpu_top_pkg.zpu_wb_bridge
32 port ( areset : in std_logic; port in zpu_top_pkg.zpu_system
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/zpu/wishbone/ |
| H A D | wishbone_pkg.vhd | 62 areset : in std_logic; port in wishbone_pkg.atomic32_access
74 areset : in std_logic; port in wishbone_pkg.eth_access_corr
|
| H A D | zpu_wb_bridge.vhd | 48 areset : in std_logic; port
|
| H A D | zpu_system.vhd | 48 port ( areset : in std_logic; port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/zpu/wishbone/ |
| H A D | wishbone_pkg.vhd | 62 areset : in std_logic; port in wishbone_pkg.atomic32_access
74 areset : in std_logic; port in wishbone_pkg.eth_access_corr
|
| H A D | zpu_wb_bridge.vhd | 48 areset : in std_logic; port
|
| H A D | zpu_system.vhd | 48 port ( areset : in std_logic; port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/zpu/core/ |
| H A D | zpupkg.vhd | 40 areset : in std_logic; port in zpupkg.dram
67 areset : in std_logic; port in zpupkg.zpu_core
86 areset : in std_logic; port in zpupkg.timer
93 port ( areset : in std_logic; port in zpupkg.zpuio
|
| H A D | zpu_core.vhd | 20 areset : in std_logic; port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/zpu/core/ |
| H A D | zpupkg.vhd | 40 areset : in std_logic; port in zpupkg.dram
67 areset : in std_logic; port in zpupkg.zpu_core
86 areset : in std_logic; port in zpupkg.timer
93 port ( areset : in std_logic; port in zpupkg.zpuio
|
| H A D | zpu_core.vhd | 20 areset : in std_logic; port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/ |
| H A D | aurora_phy_clk_gen.v | 7 input areset, port
|
| H A D | aurora_phy_x1.v | 9 input areset, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/ten_gig_eth_pcs_pma/ |
| H A D | ten_gige_phy_clk_gen.v | 7 input areset, port
|
| H A D | ten_gige_phy.v | 10 input areset, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/ |
| H A D | e310_io.v | 9 input areset, port
|
| /dports/graphics/wings/wings-8d019ebe48/src/ |
| H A D | wings_va.erl | 871 areset(_, none) -> none; function
872 areset(K, A) -> array:reset(K, A). function
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/ten_gig_eth_pcs_pma/ |
| H A D | ten_gige_phy.v | 10 input areset, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ip/ten_gig_eth_pcs_pma/ |
| H A D | ten_gige_phy.v | 10 input areset, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/ |
| H A D | aurora_phy_x1.v | 9 input areset, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
| H A D | axi_dma_master.v | 17 input areset, // Global AXI reset port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/ |
| H A D | aurora_phy_x1.v | 9 input areset, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
| H A D | x300_sfpp_io_core.v | 19 input areset, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
| H A D | n3xx_mgt_wrapper.v | 26 input wire areset, port
|