1//
2// Copyright 2008-2013 Ettus Research LLC
3//
4
5module ten_gige_phy_clk_gen
6(
7   input  areset,
8   input  refclk_p,
9   input  refclk_n,
10
11   output refclk,
12   output clk156,
13   output dclk
14);
15
16   wire clk156_buf;
17   wire dclk_buf;
18   wire clkfbout;
19
20   IBUFDS_GTE2 ibufds_inst (
21      .O     (refclk),
22      .ODIV2 (),
23      .CEB   (1'b0),
24      .I     (refclk_p),
25      .IB    (refclk_n)
26   );
27
28   BUFG clk156_bufg_inst (
29      .I (refclk),
30      .O (clk156)
31   );
32
33   // Divding independent clock by 2 as source for DRP clock
34   BUFR # (
35      .BUFR_DIVIDE ("2")
36   ) dclk_divide_by_2_buf (
37      .I   (clk156),
38      .O   (dclk_buf),
39      .CE  (1'b1),
40      .CLR (1'b0)
41   );
42
43   BUFG dclk_bufg_i (
44      .I (dclk_buf),
45      .O (dclk)
46   );
47
48endmodule
49
50
51
52