clk_ref_i (definition) in projects: dports

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Searched defs:clk_ref_i (Results 1 – 22 of 22) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_pps_gen/
H A D	xwr_pps_gen.vhd	`59 clk_ref_i : in std_logic; port 96 clk_ref_i : in std_logic; port in xwr_pps_gen.behavioral.wr_pps_gen`
H A D	wr_pps_gen.vhd	`60 clk_ref_i : in std_logic; port`
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/
H A D	streamers_pkg.vhd	`192 clk_ref_i : in std_logic := '0'; port in streamers_pkg.xtx_streamer 218 clk_ref_i : in std_logic := '0'; port in streamers_pkg.xrx_streamer 256 clk_ref_i : in std_logic; port in streamers_pkg.xrtx_streamers_stats 317 clk_ref_i : in std_logic := '0'; port in streamers_pkg.xwr_streamers`
H A D	xrtx_streamers_stats.vhd	`86 clk_ref_i : in std_logic; port`
H A D	xwr_streamers.vhd	`146 clk_ref_i : in std_logic := '0'; port`
H A D	xtx_streamer.vhd	`98 clk_ref_i : in std_logic := '0'; port`
H A D	xrx_streamer.vhd	`91 clk_ref_i : in std_logic := '0'; port`
H A D	streamers_priv_pkg.vhd	`106 clk_ref_i : in std_logic; port in streamers_priv_pkg.pulse_stamper`
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_softpll_ng/
H A D	xwr_softpll_ng.vhd	`93 clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0); port 157 clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0); port in xwr_softpll_ng.wrapper.wr_softpll_ng`
H A D	spll_aligner.vhd	`48 clk_ref_i : in std_logic; port`
H A D	wr_softpll_ng.vhd	`100 clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0); port 227 clk_ref_i : in std_logic; port in wr_softpll_ng.rtl.spll_aligner`
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/timing/
H A D	pulse_stamper.vhd	`39 clk_ref_i : in std_logic; -- timing reference clock port`
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/
H A D	ep_timestamping_unit.vhd	`70 clk_ref_i : in std_logic; port`
H A D	xwr_endpoint.vhd	`77 clk_ref_i : in std_logic; port`
H A D	endpoint_pkg.vhd	`191 clk_ref_i : in std_logic; port in endpoint_pkg.xwr_endpoint 302 clk_ref_i : in std_logic; port in endpoint_pkg.wr_endpoint`
H A D	wr_endpoint.vhd	`86 clk_ref_i : in std_logic; port`
H A D	endpoint_private_pkg.vhd	`410 clk_ref_i : in std_logic; port in endpoint_private_pkg.ep_timestamping_unit`
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wrc_core/
H A D	wrcore_pkg.vhd	`80 clk_ref_i : in std_logic; port in wrcore_pkg.xwr_pps_gen 330 clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0); port in wrcore_pkg.xwr_softpll_ng 387 clk_ref_i : in std_logic; port in wrcore_pkg.xwr_core 538 clk_ref_i : in std_logic; port in wrcore_pkg.wr_core`
H A D	xwr_core.vhd	`111 clk_ref_i : in std_logic; port`
H A D	wr_core.vhd	`112 clk_ref_i : in std_logic; port`
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/board/common/
H A D	wr_board_pkg.vhd	`125 clk_ref_i : in std_logic; port in wr_board_pkg.xwrc_board_common`
H A D	xwrc_board_common.vhd	`89 clk_ref_i : in std_logic; port`