1------------------------------------------------------------------------------- 2-- Title : WhiteRabbit PTP Core 3-- Project : WhiteRabbit 4------------------------------------------------------------------------------- 5-- File : wrcore_pkg.vhd 6-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch> 7-- Company : CERN (BE-CO-HT) 8-- Created : 2011-05-11 9-- Last update: 2017-05-29 10-- Platform : FPGA-generics 11-- Standard : VHDL 12------------------------------------------------------------------------------- 13-- 14-- Copyright (c) 2012 - 2017 CERN 15-- 16-- This source file is free software; you can redistribute it 17-- and/or modify it under the terms of the GNU Lesser General 18-- Public License as published by the Free Software Foundation; 19-- either version 2.1 of the License, or (at your option) any 20-- later version. 21-- 22-- This source is distributed in the hope that it will be 23-- useful, but WITHOUT ANY WARRANTY; without even the implied 24-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 25-- PURPOSE. See the GNU Lesser General Public License for more 26-- details. 27-- 28-- You should have received a copy of the GNU Lesser General 29-- Public License along with this source; if not, download it 30-- from http://www.gnu.org/licenses/lgpl-2.1.html 31-- 32------------------------------------------------------------------------------- 33 34library ieee; 35use ieee.std_logic_1164.all; 36 37library work; 38use work.genram_pkg.all; 39use work.wishbone_pkg.all; 40use work.sysc_wbgen2_pkg.all; 41use work.wrc_diags_wbgen2_pkg.all; 42use work.wr_fabric_pkg.all; 43use work.endpoint_pkg.all; 44use work.softpll_pkg.all; 45 46package wrcore_pkg is 47 48 function f_refclk_rate(pcs_16 : boolean) return integer; 49 50 type t_generic_word_array is array (natural range <>) of std_logic_vector(31 downto 0); 51 52 ----------------------------------------------------------------------------- 53 --PPS generator 54 ----------------------------------------------------------------------------- 55 constant c_xwr_pps_gen_sdb : t_sdb_device := ( 56 abi_class => x"0000", -- undocumented device 57 abi_ver_major => x"01", 58 abi_ver_minor => x"01", 59 wbd_endian => c_sdb_endian_big, 60 wbd_width => x"7", -- 8/16/32-bit port granularity 61 sdb_component => ( 62 addr_first => x"0000000000000000", 63 addr_last => x"00000000000000ff", 64 product => ( 65 vendor_id => x"000000000000CE42", -- CERN 66 device_id => x"de0d8ced", 67 version => x"00000001", 68 date => x"20120305", 69 name => "WR-PPS-Generator "))); 70 71 component xwr_pps_gen is 72 generic( 73 g_interface_mode : t_wishbone_interface_mode; 74 g_address_granularity : t_wishbone_address_granularity; 75 g_ref_clock_rate : integer; 76 g_ext_clock_rate : integer; 77 g_with_ext_clock_input : boolean 78 ); 79 port ( 80 clk_ref_i : in std_logic; 81 clk_sys_i : in std_logic; 82 rst_ref_n_i : in std_logic; 83 rst_sys_n_i : in std_logic; 84 slave_i : in t_wishbone_slave_in; 85 slave_o : out t_wishbone_slave_out; 86 link_ok_i : in std_logic; 87 pps_in_i : in std_logic; 88 pps_csync_o : out std_logic; 89 pps_out_o : out std_logic; 90 pps_led_o : out std_logic; 91 pps_valid_o : out std_logic; 92 tm_utc_o : out std_logic_vector(39 downto 0); 93 tm_cycles_o : out std_logic_vector(27 downto 0); 94 tm_time_valid_o : out std_logic 95 ); 96 end component; 97 98 ----------------------------------------------------------------------------- 99 --Mini NIC 100 ----------------------------------------------------------------------------- 101 constant c_xwr_mini_nic_sdb : t_sdb_device := ( 102 abi_class => x"0000", -- undocumented device 103 abi_ver_major => x"01", 104 abi_ver_minor => x"01", 105 wbd_endian => c_sdb_endian_big, 106 wbd_width => x"7", -- 8/16/32-bit port granularity 107 sdb_component => ( 108 addr_first => x"0000000000000000", 109 addr_last => x"00000000000000ff", 110 product => ( 111 vendor_id => x"000000000000CE42", -- CERN 112 device_id => x"ab28633a", 113 version => x"00000001", 114 date => x"20120305", 115 name => "WR-Mini-NIC "))); 116 117 component xwr_mini_nic 118 generic ( 119 g_interface_mode : t_wishbone_interface_mode; 120 g_address_granularity : t_wishbone_address_granularity; 121 g_tx_fifo_size : integer; 122 g_rx_fifo_size : integer; 123 g_buffer_little_endian : boolean); 124 port ( 125 clk_sys_i : in std_logic; 126 rst_n_i : in std_logic; 127 src_o : out t_wrf_source_out; 128 src_i : in t_wrf_source_in; 129 snk_o : out t_wrf_sink_out; 130 snk_i : in t_wrf_sink_in; 131 txtsu_port_id_i : in std_logic_vector(4 downto 0); 132 txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0); 133 txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0); 134 txtsu_tsincorrect_i : in std_logic; 135 txtsu_stb_i : in std_logic; 136 txtsu_ack_o : out std_logic; 137 wb_i : in t_wishbone_slave_in; 138 wb_o : out t_wishbone_slave_out); 139 end component; 140 141 ----------------------------------------------------------------------------- 142 -- PERIPHERIALS 143 ----------------------------------------------------------------------------- 144 component xwr_diags_wb is 145 generic( 146 g_interface_mode : t_wishbone_interface_mode := CLASSIC; 147 g_address_granularity : t_wishbone_address_granularity := WORD 148 ); 149 port ( 150 rst_n_i : in std_logic; 151 clk_sys_i : in std_logic; 152 153 slave_i : in t_wishbone_slave_in; 154 slave_o : out t_wishbone_slave_out; 155 156 regs_i : in t_wrc_diags_in_registers; 157 regs_o : out t_wrc_diags_out_registers 158 ); 159 end component; 160 161 constant c_wrc_periph0_sdb : t_sdb_device := ( 162 abi_class => x"0000", -- undocumented device 163 abi_ver_major => x"01", 164 abi_ver_minor => x"01", 165 wbd_endian => c_sdb_endian_big, 166 wbd_width => x"7", -- 8/16/32-bit port granularity 167 sdb_component => ( 168 addr_first => x"0000000000000000", 169 addr_last => x"00000000000000ff", 170 product => ( 171 vendor_id => x"000000000000CE42", -- CERN 172 device_id => x"ff07fc47", 173 version => x"00000001", 174 date => x"20120305", 175 name => "WR-Periph-Syscon "))); 176 177 constant c_wrc_periph1_sdb : t_sdb_device := ( 178 abi_class => x"0000", -- undocumented device 179 abi_ver_major => x"01", 180 abi_ver_minor => x"01", 181 wbd_endian => c_sdb_endian_big, 182 wbd_width => x"7", -- 8/16/32-bit port granularity 183 sdb_component => ( 184 addr_first => x"0000000000000000", 185 addr_last => x"00000000000000ff", 186 product => ( 187 vendor_id => x"000000000000CE42", -- CERN 188 device_id => x"e2d13d04", 189 version => x"00000001", 190 date => x"20120305", 191 name => "WR-Periph-UART "))); 192 193 constant c_wrc_periph2_sdb : t_sdb_device := ( 194 abi_class => x"0000", -- undocumented device 195 abi_ver_major => x"01", 196 abi_ver_minor => x"01", 197 wbd_endian => c_sdb_endian_big, 198 wbd_width => x"7", -- 8/16/32-bit port granularity 199 sdb_component => ( 200 addr_first => x"0000000000000000", 201 addr_last => x"00000000000000ff", 202 product => ( 203 vendor_id => x"000000000000CE42", -- CERN 204 device_id => x"779c5443", 205 version => x"00000001", 206 date => x"20120305", 207 name => "WR-Periph-1Wire "))); 208 209 210 constant c_wrc_periph3_sdb : t_sdb_device := ( 211 abi_class => x"0000", -- undocumented device 212 abi_ver_major => x"01", 213 abi_ver_minor => x"01", 214 wbd_endian => c_sdb_endian_big, 215 wbd_width => x"7", -- 8/16/32-bit port granularity 216 sdb_component => ( 217 addr_first => x"0000000000000000", 218 addr_last => x"00000000000000ff", 219 product => ( 220 vendor_id => x"000000000000CE42", -- CERN 221 device_id => x"779c5445", 222 version => x"00000001", 223 date => x"20120615", 224 name => "WR-Periph-AuxWB "))); 225 226 constant c_wrc_periph4_sdb : t_sdb_device := ( 227 abi_class => x"0000", -- undocumented device 228 abi_ver_major => x"01", 229 abi_ver_minor => x"01", 230 wbd_endian => c_sdb_endian_big, 231 wbd_width => x"7", -- 8/16/32-bit port granularity 232 sdb_component => ( 233 addr_first => x"0000000000000000", 234 addr_last => x"00000000000000ff", 235 product => ( 236 vendor_id => x"000000000000CE42", -- CERN 237 device_id => x"779c5446", 238 version => x"00000001", 239 date => x"20170424", 240 name => "WR-Periph-WRPC-DIAG"))); 241 242 component wrc_periph is 243 generic( 244 g_board_name : string := "NA "; 245 g_flash_secsz_kb : integer := 64; 246 g_flash_sdbfs_baddr : integer := 16#2e0000#; 247 g_phys_uart : boolean := true; 248 g_virtual_uart : boolean := false; 249 g_cntr_period : integer := 62500; 250 g_mem_words : integer := 16384; 251 g_vuart_fifo_size : integer := 1024; 252 g_diag_id : integer := 0; 253 g_diag_ver : integer := 0; 254 g_diag_ro_size : integer := 0; 255 g_diag_rw_size : integer := 0 256 ); 257 port( 258 clk_sys_i : in std_logic; 259 rst_n_i : in std_logic; 260 rst_net_n_o : out std_logic; 261 rst_wrc_n_o : out std_logic; 262 led_red_o : out std_logic; 263 led_green_o : out std_logic; 264 scl_o : out std_logic; 265 scl_i : in std_logic; 266 sda_o : out std_logic; 267 sda_i : in std_logic; 268 sfp_scl_o : out std_logic; 269 sfp_scl_i : in std_logic; 270 sfp_sda_o : out std_logic; 271 sfp_sda_i : in std_logic; 272 sfp_det_i : in std_logic; 273 memsize_i : in std_logic_vector(3 downto 0); 274 btn1_i : in std_logic; 275 btn2_i : in std_logic; 276 spi_sclk_o : out std_logic; 277 spi_ncs_o : out std_logic; 278 spi_mosi_o : out std_logic; 279 spi_miso_i : in std_logic; 280 slave_i : in t_wishbone_slave_in_array(0 to 3); 281 slave_o : out t_wishbone_slave_out_array(0 to 3); 282 uart_rxd_i : in std_logic; 283 uart_txd_o : out std_logic; 284 owr_pwren_o : out std_logic_vector(1 downto 0); 285 owr_en_o : out std_logic_vector(1 downto 0); 286 owr_i : in std_logic_vector(1 downto 0); 287 diag_array_in : in t_generic_word_array(g_diag_ro_size-1 downto 0); 288 diag_array_out : out t_generic_word_array(g_diag_rw_size-1 downto 0) 289 ); 290 end component; 291 292 ----------------------------------------------------------------------------- 293 -- Soft-PLL 294 ----------------------------------------------------------------------------- 295 constant c_xwr_softpll_ng_sdb : t_sdb_device := ( 296 abi_class => x"0000", -- undocumented device 297 abi_ver_major => x"01", 298 abi_ver_minor => x"01", 299 wbd_endian => c_sdb_endian_big, 300 wbd_width => x"7", -- 8/16/32-bit port granularity 301 sdb_component => ( 302 addr_first => x"0000000000000000", 303 addr_last => x"00000000000000ff", 304 product => ( 305 vendor_id => x"000000000000CE42", -- CERN 306 device_id => x"65158dc0", 307 version => x"00000002", 308 date => x"20120305", 309 name => "WR-Soft-PLL "))); 310 311 component xwr_softpll_ng 312 generic ( 313 g_tag_bits : integer; 314 g_num_ref_inputs : integer; 315 g_num_outputs : integer; 316 g_with_debug_fifo : boolean; 317 g_with_ext_clock_input : boolean; 318 g_reverse_dmtds : boolean; 319 g_divide_input_by_2 : boolean; 320 g_ref_clock_rate : integer; 321 g_ext_clock_rate : integer; 322 g_interface_mode : t_wishbone_interface_mode; 323 g_address_granularity : t_wishbone_address_granularity); 324 port ( 325 clk_sys_i : in std_logic; 326 rst_sys_n_i : in std_logic; 327 rst_ref_n_i : in std_logic; 328 rst_ext_n_i : in std_logic; 329 rst_dmtd_n_i : in std_logic; 330 clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0); 331 clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0); 332 clk_dmtd_i : in std_logic; 333 clk_ext_i : in std_logic; 334 clk_ext_mul_i : in std_logic; 335 clk_ext_mul_locked_i : in std_logic; 336 clk_ext_stopped_i : in std_logic; 337 clk_ext_rst_o : out std_logic; 338 pps_csync_p1_i : in std_logic; 339 pps_ext_a_i : in std_logic; 340 dac_dmtd_data_o : out std_logic_vector(15 downto 0); 341 dac_dmtd_load_o : out std_logic; 342 dac_out_data_o : out std_logic_vector(15 downto 0); 343 dac_out_sel_o : out std_logic_vector(3 downto 0); 344 dac_out_load_o : out std_logic; 345 out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0); 346 out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0); 347 slave_i : in t_wishbone_slave_in; 348 slave_o : out t_wishbone_slave_out; 349 debug_o : out std_logic_vector(5 downto 0); 350 dbg_fifo_irq_o : out std_logic); 351 end component; 352 353 constant cc_unused_master_in : t_wishbone_master_in := 354 ('1', '0', '0', '0', '0', cc_dummy_data); 355 356 ----------------------------------------------------------------------------- 357 -- Public WR component definitions 358 ----------------------------------------------------------------------------- 359 component xwr_core is 360 generic( 361 g_simulation : integer := 0; 362 g_board_name : string := "NA "; 363 g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128) 364 g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128) 365 g_phys_uart : boolean := true; 366 g_virtual_uart : boolean := true; 367 g_with_external_clock_input : boolean := true; 368 g_aux_clks : integer := 0; 369 g_ep_rxbuf_size : integer := 1024; 370 g_tx_runt_padding : boolean := true; 371 g_dpram_initf : string := "default"; 372 g_dpram_size : integer := 131072/4; --in 32-bit words 373 g_interface_mode : t_wishbone_interface_mode := PIPELINED; 374 g_address_granularity : t_wishbone_address_granularity := BYTE; 375 g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb; 376 g_softpll_enable_debugger : boolean := false; 377 g_vuart_fifo_size : integer := 1024; 378 g_pcs_16bit : boolean := false; 379 g_records_for_phy : boolean := false; 380 g_diag_id : integer := 0; 381 g_diag_ver : integer := 0; 382 g_diag_ro_size : integer := 0; 383 g_diag_rw_size : integer := 0); 384 port( 385 clk_sys_i : in std_logic; 386 clk_dmtd_i : in std_logic := '0'; 387 clk_ref_i : in std_logic; 388 clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0'); 389 clk_ext_mul_i : in std_logic := '0'; 390 clk_ext_mul_locked_i : in std_logic := '1'; 391 clk_ext_stopped_i : in std_logic := '0'; 392 clk_ext_rst_o : out std_logic; 393 clk_ext_i : in std_logic := '0'; 394 pps_ext_i : in std_logic := '0'; 395 rst_n_i : in std_logic; 396 397 dac_hpll_load_p1_o : out std_logic; 398 dac_hpll_data_o : out std_logic_vector(15 downto 0); 399 dac_dpll_load_p1_o : out std_logic; 400 dac_dpll_data_o : out std_logic_vector(15 downto 0); 401 ----------------------------------------- 402 -- PHY I/f 403 ----------------------------------------- 404 phy_ref_clk_i : in std_logic := '0'; 405 phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0); 406 phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0); 407 phy_tx_disparity_i : in std_logic := '0'; 408 phy_tx_enc_err_i : in std_logic := '0'; 409 phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0'); 410 phy_rx_rbclk_i : in std_logic := '0'; 411 phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0'); 412 phy_rx_enc_err_i : in std_logic := '0'; 413 phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0'); 414 phy_rst_o : out std_logic; 415 phy_rdy_i : in std_logic := '1'; 416 phy_loopen_o : out std_logic; 417 phy_loopen_vec_o : out std_logic_vector(2 downto 0); 418 phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0); 419 phy_sfp_tx_fault_i : in std_logic := '0'; 420 phy_sfp_los_i : in std_logic := '0'; 421 phy_sfp_tx_disable_o : out std_logic; 422 ----------------------------------------- 423 -- PHY I/f - record-based 424 -- selection done with g_records_for_phy 425 ----------------------------------------- 426 phy8_o : out t_phy_8bits_from_wrc; 427 phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc; 428 phy16_o : out t_phy_16bits_from_wrc; 429 phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc; 430 431 led_act_o : out std_logic; 432 led_link_o : out std_logic; 433 scl_o : out std_logic; 434 scl_i : in std_logic := 'H'; 435 sda_o : out std_logic; 436 sda_i : in std_logic := 'H'; 437 sfp_scl_o : out std_logic; 438 sfp_scl_i : in std_logic := 'H'; 439 sfp_sda_o : out std_logic; 440 sfp_sda_i : in std_logic := 'H'; 441 sfp_det_i : in std_logic := '1'; 442 btn1_i : in std_logic := 'H'; 443 btn2_i : in std_logic := 'H'; 444 spi_sclk_o : out std_logic; 445 spi_ncs_o : out std_logic; 446 spi_mosi_o : out std_logic; 447 spi_miso_i : in std_logic := '0'; 448 449 uart_rxd_i : in std_logic := 'H'; 450 uart_txd_o : out std_logic; 451 452 owr_pwren_o : out std_logic_vector(1 downto 0); 453 owr_en_o : out std_logic_vector(1 downto 0); 454 owr_i : in std_logic_vector(1 downto 0) := "HH"; 455 456 slave_i : in t_wishbone_slave_in := cc_dummy_slave_in; 457 slave_o : out t_wishbone_slave_out; 458 459 aux_master_o : out t_wishbone_master_out; 460 aux_master_i : in t_wishbone_master_in := cc_unused_master_in; 461 462 wrf_src_o : out t_wrf_source_out; 463 wrf_src_i : in t_wrf_source_in := c_dummy_src_in; 464 wrf_snk_o : out t_wrf_sink_out; 465 wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in; 466 467 timestamps_o : out t_txtsu_timestamp; 468 timestamps_ack_i : in std_logic := '1'; 469 470 abscal_txts_o : out std_logic; 471 abscal_rxts_o : out std_logic; 472 473 fc_tx_pause_req_i : in std_logic := '0'; 474 fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000"; 475 fc_tx_pause_ready_o : out std_logic; 476 477 tm_link_up_o : out std_logic; 478 tm_dac_value_o : out std_logic_vector(23 downto 0); 479 tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0); 480 tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0'); 481 tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0); 482 tm_time_valid_o : out std_logic; 483 tm_tai_o : out std_logic_vector(39 downto 0); 484 tm_cycles_o : out std_logic_vector(27 downto 0); 485 pps_csync_o : out std_logic; 486 pps_p_o : out std_logic; 487 pps_led_o : out std_logic; 488 489 rst_aux_n_o : out std_logic; 490 491 link_ok_o : out std_logic; 492 493 aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0')); 494 aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0) 495 ); 496 end component; 497 498 component wr_core is 499 generic( 500 --if set to 1, then blocks in PCS use smaller calibration counter to speed 501 --up simulation 502 g_simulation : integer := 0; 503 g_with_external_clock_input : boolean := true; 504 -- 505 g_board_name : string := "NA "; 506 g_flash_secsz_kb : integer := 256; -- default for SVEC (M25P128) 507 g_flash_sdbfs_baddr : integer := 16#600000#; -- default for SVEC (M25P128) 508 g_phys_uart : boolean := true; 509 g_virtual_uart : boolean := true; 510 g_aux_clks : integer := 0; 511 g_rx_buffer_size : integer := 1024; 512 g_tx_runt_padding : boolean := true; 513 g_dpram_initf : string := "default"; 514 g_dpram_size : integer := 131072/4; --in 32-bit words 515 g_interface_mode : t_wishbone_interface_mode := PIPELINED; 516 g_address_granularity : t_wishbone_address_granularity := BYTE; 517 g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb; 518 g_softpll_enable_debugger : boolean := false; 519 g_vuart_fifo_size : integer := 1024; 520 g_pcs_16bit : boolean := false; 521 g_records_for_phy : boolean := false; 522 g_diag_id : integer := 0; 523 g_diag_ver : integer := 0; 524 g_diag_ro_size : integer := 0; 525 g_diag_rw_size : integer := 0); 526 port( 527 --------------------------------------------------------------------------- 528 -- Clocks/resets 529 --------------------------------------------------------------------------- 530 531 -- system reference clock (any frequency <= f(clk_ref_i)) 532 clk_sys_i : in std_logic; 533 534 -- DDMTD offset clock (125.x MHz) 535 clk_dmtd_i : in std_logic := '0'; 536 537 -- Timing reference (125 MHz) 538 clk_ref_i : in std_logic; 539 540 -- Aux clocks (i.e. the FMC clock), which can be disciplined by the WR Core 541 clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0'); 542 543 -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode 544 clk_ext_i : in std_logic := '0'; 545 546 clk_ext_mul_i : in std_logic := '0'; 547 clk_ext_mul_locked_i : in std_logic := '1'; 548 clk_ext_stopped_i : in std_logic := '0'; 549 clk_ext_rst_o : out std_logic; 550 551 -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode 552 pps_ext_i : in std_logic := '0'; 553 554 rst_n_i : in std_logic; 555 556 ----------------------------------------- 557 --Timing system 558 ----------------------------------------- 559 dac_hpll_load_p1_o : out std_logic; 560 dac_hpll_data_o : out std_logic_vector(15 downto 0); 561 562 dac_dpll_load_p1_o : out std_logic; 563 dac_dpll_data_o : out std_logic_vector(15 downto 0); 564 565 ----------------------------------------- 566 -- PHY I/f 567 ----------------------------------------- 568 phy_ref_clk_i : in std_logic; 569 570 phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0); 571 phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0); 572 phy_tx_disparity_i : in std_logic := '0'; 573 phy_tx_enc_err_i : in std_logic := '0'; 574 575 phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0'); 576 phy_rx_rbclk_i : in std_logic := '0'; 577 phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0):= (others=>'0'); 578 phy_rx_enc_err_i : in std_logic := '0'; 579 phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0'); 580 581 phy_rst_o : out std_logic; 582 phy_rdy_i : in std_logic := '1'; 583 phy_loopen_o : out std_logic; 584 phy_loopen_vec_o : out std_logic_vector(2 downto 0); 585 phy_tx_prbs_sel_o : out std_logic_vector(2 downto 0); 586 phy_sfp_tx_fault_i : in std_logic := '0'; 587 phy_sfp_los_i : in std_logic := '0'; 588 phy_sfp_tx_disable_o : out std_logic; 589 ----------------------------------------- 590 -- PHY I/f - record-based 591 -- selection done with g_records_for_phy 592 ----------------------------------------- 593 phy8_o : out t_phy_8bits_from_wrc; 594 phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc; 595 phy16_o : out t_phy_16bits_from_wrc; 596 phy16_i : in t_phy_16bits_to_wrc := c_dummy_phy16_to_wrc; 597 598 ----------------------------------------- 599 --GPIO 600 ----------------------------------------- 601 led_act_o : out std_logic; 602 led_link_o : out std_logic; 603 scl_o : out std_logic; 604 scl_i : in std_logic := '1'; 605 sda_o : out std_logic; 606 sda_i : in std_logic := '1'; 607 sfp_scl_o : out std_logic; 608 sfp_scl_i : in std_logic := '1'; 609 sfp_sda_o : out std_logic; 610 sfp_sda_i : in std_logic := '1'; 611 sfp_det_i : in std_logic := '1'; 612 btn1_i : in std_logic := '1'; 613 btn2_i : in std_logic := '1'; 614 spi_sclk_o : out std_logic; 615 spi_ncs_o : out std_logic; 616 spi_mosi_o : out std_logic; 617 spi_miso_i : in std_logic := '0'; 618 619 ----------------------------------------- 620 --UART 621 ----------------------------------------- 622 uart_rxd_i : in std_logic := '0'; 623 uart_txd_o : out std_logic; 624 625 ----------------------------------------- 626 -- 1-wire 627 ----------------------------------------- 628 owr_pwren_o : out std_logic_vector(1 downto 0); 629 owr_en_o : out std_logic_vector(1 downto 0); 630 owr_i : in std_logic_vector(1 downto 0) := (others => '1'); 631 632 ----------------------------------------- 633 --External WB interface 634 ----------------------------------------- 635 wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0'); 636 wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0'); 637 wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0); 638 wb_sel_i : in std_logic_vector(c_wishbone_address_width/8-1 downto 0) := (others => '0'); 639 wb_we_i : in std_logic := '0'; 640 wb_cyc_i : in std_logic := '0'; 641 wb_stb_i : in std_logic := '0'; 642 wb_ack_o : out std_logic; 643 wb_err_o : out std_logic; 644 wb_rty_o : out std_logic; 645 wb_stall_o : out std_logic; 646 647 ----------------------------------------- 648 -- Auxillary WB master 649 ----------------------------------------- 650 aux_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0); 651 aux_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0); 652 aux_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0'); 653 aux_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0); 654 aux_we_o : out std_logic; 655 aux_cyc_o : out std_logic; 656 aux_stb_o : out std_logic; 657 aux_ack_i : in std_logic := '1'; 658 aux_stall_i : in std_logic := '0'; 659 660 ----------------------------------------- 661 -- External Fabric I/F 662 ----------------------------------------- 663 ext_snk_adr_i : in std_logic_vector(1 downto 0) := "00"; 664 ext_snk_dat_i : in std_logic_vector(15 downto 0) := x"0000"; 665 ext_snk_sel_i : in std_logic_vector(1 downto 0) := "00"; 666 ext_snk_cyc_i : in std_logic := '0'; 667 ext_snk_we_i : in std_logic := '0'; 668 ext_snk_stb_i : in std_logic := '0'; 669 ext_snk_ack_o : out std_logic; 670 ext_snk_err_o : out std_logic; 671 ext_snk_stall_o : out std_logic; 672 673 ext_src_adr_o : out std_logic_vector(1 downto 0); 674 ext_src_dat_o : out std_logic_vector(15 downto 0); 675 ext_src_sel_o : out std_logic_vector(1 downto 0); 676 ext_src_cyc_o : out std_logic; 677 ext_src_stb_o : out std_logic; 678 ext_src_we_o : out std_logic; 679 ext_src_ack_i : in std_logic := '1'; 680 ext_src_err_i : in std_logic := '0'; 681 ext_src_stall_i : in std_logic := '0'; 682 683 ------------------------------------------ 684 -- External TX Timestamp I/F 685 ------------------------------------------ 686 txtsu_port_id_o : out std_logic_vector(4 downto 0); 687 txtsu_frame_id_o : out std_logic_vector(15 downto 0); 688 txtsu_ts_value_o : out std_logic_vector(31 downto 0); 689 txtsu_ts_incorrect_o : out std_logic; 690 txtsu_stb_o : out std_logic; 691 txtsu_ack_i : in std_logic := '1'; 692 693 ----------------------------------------- 694 -- Timestamp helper signals, used for Absolute Calibration 695 ----------------------------------------- 696 abscal_txts_o : out std_logic; 697 abscal_rxts_o : out std_logic; 698 699 ----------------------------------------- 700 -- Pause Frame Control 701 ----------------------------------------- 702 fc_tx_pause_req_i : in std_logic := '0'; 703 fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000"; 704 fc_tx_pause_ready_o : out std_logic; 705 706 ----------------------------------------- 707 -- Timecode/Servo Control 708 ----------------------------------------- 709 710 tm_link_up_o : out std_logic; 711 712 tm_dac_value_o : out std_logic_vector(23 downto 0); 713 tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0) ; 714 tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0'); 715 tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0) ; 716 717 -- Timecode output 718 tm_time_valid_o : out std_logic; 719 tm_tai_o : out std_logic_vector(39 downto 0); 720 tm_cycles_o : out std_logic_vector(27 downto 0); 721 -- 1PPS output 722 pps_csync_o : out std_logic; 723 pps_p_o : out std_logic; 724 pps_led_o : out std_logic; 725 726 rst_aux_n_o : out std_logic; 727 728 link_ok_o : out std_logic; 729 730 ------------------------------------- 731 -- DIAG to/from external modules 732 ------------------------------------- 733 aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others=>(others=>'0')); 734 aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0) 735 ); 736 end component; 737 738 component spec_serial_dac_arb 739 generic( 740 g_invert_sclk : boolean; 741 g_num_extra_bits : integer); 742 port ( 743 clk_i : in std_logic; 744 rst_n_i : in std_logic; 745 val1_i : in std_logic_vector(15 downto 0); 746 load1_i : in std_logic; 747 val2_i : in std_logic_vector(15 downto 0); 748 load2_i : in std_logic; 749 dac_cs_n_o : out std_logic_vector(1 downto 0); 750 dac_clr_n_o : out std_logic; 751 dac_sclk_o : out std_logic; 752 dac_din_o : out std_logic); 753 end component; 754 755end wrcore_pkg; 756 757package body wrcore_pkg is 758 759 function f_refclk_rate(pcs_16 : boolean) 760 return integer is 761 begin 762 if (pcs_16) then 763 return 62500000; 764 else 765 return 125000000; 766 end if; 767 end function; 768 769end package body wrcore_pkg; 770