1 /* $OpenBSD: if_myxreg.h,v 1.13 2019/04/15 02:59:41 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Register definitions for the Myricom Myri-10G Lanai-Z8E Ethernet chipsets. 21 */ 22 23 #ifndef _MYX_REG_H 24 #define _MYX_REG_H 25 26 /* 27 * Common definitions 28 */ 29 30 #define MYXBAR0 PCI_MAPREG_START 31 32 #define MYX_NRXDESC 256 33 #define MYX_NTXDESC_MIN 2 34 #define MYX_IRQCOALDELAY 60 35 #define MYX_IRQDEASSERTWAIT 1 36 37 #define MYXALIGN_CMD 64 38 #define MYXALIGN_DATA PAGE_SIZE 39 #define MYX_BOUNDARY 4096 40 #define MYX_MTU 9400 41 42 #define MYX_ADDRHIGH(_v) (((u_int64_t)_v >> 32) & 0xffffffff) 43 #define MYX_ADDRLOW(_v) ((u_int64_t)_v & 0xffffffff) 44 45 /* 46 * PCI memory/register layout 47 */ 48 49 #define MYX_SRAM 0x00000000 /* SRAM offset */ 50 #define MYX_SRAM_SIZE 0x001dff00 /* SRAM size */ 51 #define MYX_HEADER_POS 0x0000003c /* Header position offset */ 52 #define MYX_HEADER_POS_SIZE 0x00000004 /* Header position size */ 53 #define MYX_FW 0x00100000 /* Firmware offset */ 54 #define MYX_FW_BOOT 0x00100008 /* Firmware boot offset */ 55 #define MYX_STRING_SPECS 0x001dfe00 /* STRING_SPECS offset */ 56 #define MYX_STRING_SPECS_SIZE 0x00000100 /* STRING_SPECS size */ 57 #define MYX_BOOT 0x00fc0000 /* Boot handoff */ 58 #define MYX_RDMA 0x00fc01c0 /* Dummy RDMA */ 59 #define MYX_CMD 0x00f80000 /* Command offset */ 60 61 /* 62 * Firmware definitions 63 */ 64 65 #define MYXFW_ALIGNED "myx-eth_z8e" 66 #define MYXFW_UNALIGNED "myx-ethp_z8e" 67 #define MYXFW_TYPE_ETH 0x45544820 68 #define MYXFW_VER "1.4." /* stored as a string... */ 69 70 #define MYXFW_MIN_LEN (MYX_HEADER_POS + MYX_HEADER_POS_SIZE) 71 72 struct myx_gen_hdr { 73 u_int32_t fw_hdrlength; 74 u_int32_t fw_type; 75 u_int8_t fw_version[128]; 76 u_int32_t fw_mcp_globals; 77 u_int32_t fw_sram_size; 78 u_int32_t fw_specs; 79 u_int32_t fw_specs_len; 80 } __packed; 81 82 /* 83 * Commands, descriptors, and DMA structures 84 */ 85 86 struct myx_cmd { 87 u_int32_t mc_cmd; 88 u_int32_t mc_data0; 89 u_int32_t mc_data1; 90 u_int32_t mc_data2; 91 u_int32_t mc_addr_high; 92 u_int32_t mc_addr_low; 93 u_int8_t mc_pad[40]; /* pad up to 64 bytes */ 94 } __packed __aligned(4); 95 96 struct myx_response { 97 u_int32_t mr_data; 98 u_int32_t mr_result; 99 } __packed; 100 101 struct myx_bootcmd { 102 u_int32_t bc_addr_high; 103 u_int32_t bc_addr_low; 104 u_int32_t bc_result; 105 u_int32_t bc_offset; 106 u_int32_t bc_length; 107 u_int32_t bc_copyto; 108 u_int32_t bc_jumpto; 109 u_int8_t bc_pad[36]; /* pad up to 64 bytes */ 110 } __packed; 111 112 struct myx_rdmacmd { 113 u_int32_t rc_addr_high; 114 u_int32_t rc_addr_low; 115 u_int32_t rc_result; 116 u_int32_t rc_rdma_high; 117 u_int32_t rc_rdma_low; 118 u_int32_t rc_enable; 119 #define MYXRDMA_ON 1 120 #define MYXRDMA_OFF 0 121 u_int8_t rc_pad[40]; /* pad up to 64 bytes */ 122 } __packed; 123 124 struct myx_status { 125 u_int32_t ms_reserved; 126 u_int32_t ms_dropped_pause; 127 u_int32_t ms_dropped_unicast; 128 u_int32_t ms_dropped_crc32err; 129 u_int32_t ms_dropped_phyerr; 130 u_int32_t ms_dropped_mcast; 131 u_int32_t ms_txdonecnt; 132 u_int32_t ms_linkstate; 133 #define MYXSTS_LINKDOWN 0 134 #define MYXSTS_LINKUP 1 135 #define MYXSTS_LINKUNKNOWN 2 136 u_int32_t ms_dropped_linkoverflow; 137 u_int32_t ms_dropped_linkerror; 138 u_int32_t ms_dropped_runt; 139 u_int32_t ms_dropped_overrun; 140 u_int32_t ms_dropped_smallbufunderrun; 141 u_int32_t ms_dropped_bigbufunderrun; 142 u_int32_t ms_rdmatags_available; 143 #define MYXSTS_RDMAON 1 144 #define MYXSTS_RDMAOFF 0 145 u_int8_t ms_txstopped; 146 u_int8_t ms_linkdown; 147 u_int8_t ms_statusupdated; 148 u_int8_t ms_isvalid; 149 } __packed __aligned(4); 150 151 struct myx_intrq_desc { 152 u_int16_t iq_csum; 153 u_int16_t iq_length; 154 } __packed __aligned(4); 155 156 struct myx_rx_desc { 157 u_int64_t rx_addr; 158 } __packed __aligned(8); 159 160 struct myx_tx_desc { 161 u_int64_t tx_addr; 162 u_int16_t tx_hdr_offset; 163 u_int16_t tx_length; 164 u_int8_t tx_pad; 165 u_int8_t tx_nsegs; 166 u_int8_t tx_cksum_offset; 167 u_int8_t tx_flags; 168 #define MYXTXD_FLAGS_SMALL (1<<0) 169 #define MYXTXD_FLAGS_FIRST (1<<1) 170 #define MYXTXD_FLAGS_ALIGN_ODD (1<<2) 171 #define MYXTXD_FLAGS_CKSUM (1<<3) 172 #define MYXTXD_FLAGS_NO_TSO (1<<4) 173 174 #define MYXTXD_FLAGS_TSO_HDR (1<<0) 175 #define MYXTXD_FLAGS_TSO_LAST (1<<3) 176 #define MYXTXD_FLAGS_TSO_CHOP (1<<4) 177 #define MYXTXD_FLAGS_TSO_PLD (1<<5) 178 } __packed __aligned(8); 179 180 enum { 181 MYXCMD_NONE = 0, 182 MYXCMD_RESET = 1, 183 MYXCMD_GET_VERSION = 2, 184 MYXCMD_SET_INTRQDMA = 3, 185 MYXCMD_SET_BIGBUFSZ = 4, 186 MYXCMD_SET_SMALLBUFSZ = 5, 187 MYXCMD_GET_TXRINGOFF = 6, 188 MYXCMD_GET_RXSMALLRINGOFF = 7, 189 MYXCMD_GET_RXBIGRINGOFF = 8, 190 MYXCMD_GET_INTRACKOFF = 9, 191 MYXCMD_GET_INTRDEASSERTOFF = 10, 192 MYXCMD_GET_TXRINGSZ = 11, 193 MYXCMD_GET_RXRINGSZ = 12, 194 MYXCMD_SET_INTRQSZ = 13, 195 MYXCMD_SET_IFUP = 14, 196 MYXCMD_SET_IFDOWN = 15, 197 MYXCMD_SET_MTU = 16, 198 MYXCMD_GET_INTRCOALDELAYOFF = 17, 199 MYXCMD_SET_STATSINTVL = 18, 200 MYXCMD_SET_STATSDMA_OLD = 19, 201 MYXCMD_SET_PROMISC = 20, 202 MYXCMD_UNSET_PROMISC = 21, 203 MYXCMD_SET_LLADDR = 22, 204 MYXCMD_SET_FC = 23, 205 MYXCMD_UNSET_FC = 24, 206 #define MYXCMD_FC_DEFAULT MYXCMD_SET_FC /* set flow control */ 207 MYXCMD_DMA_TEST = 25, 208 MYXCMD_SET_ALLMULTI = 26, 209 MYXCMD_UNSET_ALLMULTI = 27, 210 MYXCMD_SET_MCASTGROUP = 28, 211 MYXCMD_UNSET_MCASTGROUP = 29, 212 MYXCMD_UNSET_MCAST = 30, 213 MYXCMD_SET_STATSDMA = 31, 214 MYXCMD_UNALIGNED_DMA_TEST = 32, 215 MYXCMD_GET_UNALIGNED_STATUS = 33, 216 MYXCMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 217 MYXCMD_GET_MAX_RSS_QUEUES = 35, 218 MYXCMD_ENABLE_RSS_QUEUES = 36, 219 MYXCMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET 220 = 37, 221 MYXCMD_SET_RSS_SHARED_INTERRUPT_DMA 222 = 38, 223 MYXCMD_GET_RSS_TABLE_OFFSET = 39, 224 MYXCMD_SET_RSS_TABLE_SIZE = 40, 225 MYXCMD_GET_RSS_KEY_OFFSET = 41, 226 MYXCMD_RSS_KEY_UPDATED = 42, 227 MYXCMD_SET_RSS_ENABLE = 43, 228 MYXCMD_GET_MAX_TSO6_HDR_SIZE = 44, 229 MYXCMD_SET_TSO_MODE = 45, 230 MYXCMD_MDIO_READ = 46, 231 MYXCMD_MDIO_WRITE = 47, 232 MYXCMD_I2C_READ = 48, 233 MYXCMD_I2C_BYTE = 49, 234 MYXCMD_GET_VPUMP_OFFSET = 50, 235 MYXCMD_RESET_VPUMP = 51, 236 MYXCMD_SET_RSS_MCP_SLOT_TYPE = 52, 237 MYXCMD_SET_THROTTLE_FACTOR = 53, 238 MYXCMD_VPUMP_UP = 54, 239 MYXCMD_GET_VPUMP_CLK = 55, 240 MYXCMD_GET_DCA_OFFSET = 56, 241 MYXCMD_NETQ_GET_FILTERS_PER_QUEUE 242 = 57, 243 MYXCMD_NETQ_ADD_FILTER = 58, 244 MYXCMD_NETQ_DEL_FILTER = 59, 245 MYXCMD_NETQ_QUERY1 = 60, 246 MYXCMD_NETQ_QUERY2 = 61, 247 MYXCMD_NETQ_QUERY3 = 62, 248 MYXCMD_NETQ_QUERY4 = 63, 249 MYXCMD_RELAX_RXBUFFER_ALIGNMENT = 64, 250 }; 251 252 enum { 253 MYXCMD_OK = 0, 254 MYXCMD_UNKNOWN = 1, 255 MYXCMD_ERR_RANGE = 2, 256 MYXCMD_ERR_BUSY = 3, 257 MYXCMD_ERR_EMPTY = 4, 258 MYXCMD_ERR_CLOSED = 5, 259 MYXCMD_ERR_HASH = 6, 260 MYXCMD_ERR_BADPORT = 7, 261 MYXCMD_ERR_RES = 8, 262 MYXCMD_ERR_MULTICAST = 9, 263 MYXCMD_ERR_UNALIGNED = 10, 264 MYXCMD_ERR_NO_MDIO = 11, 265 MYXCMD_ERR_I2C_FAILURE = 12, 266 MYXCMD_ERR_I2C_ABSENT = 13, 267 MYXCMD_ERR_BAD_PCIE_LINK = 14, 268 }; 269 270 #endif /* _MYX_REG_H */ 271