Searched hist:"0 af312b6" (Results 1 – 5 of 5) sorted by relevance
/qemu/target/arm/ |
H A D | cpu-param.h | 0af312b6 Tue Mar 01 21:59:49 GMT 2022 Richard Henderson <richard.henderson@linaro.org> target/arm: Implement FEAT_LVA
This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size).
Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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H A D | cpu64.c | 0af312b6 Tue Mar 01 21:59:49 GMT 2022 Richard Henderson <richard.henderson@linaro.org> target/arm: Implement FEAT_LVA
This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size).
Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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H A D | cpu.h | 0af312b6 Tue Mar 01 21:59:49 GMT 2022 Richard Henderson <richard.henderson@linaro.org> target/arm: Implement FEAT_LVA
This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size).
Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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H A D | helper.c | 0af312b6 Tue Mar 01 21:59:49 GMT 2022 Richard Henderson <richard.henderson@linaro.org> target/arm: Implement FEAT_LVA
This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size).
Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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/qemu/docs/system/arm/ |
H A D | emulation.rst | 0af312b6 Tue Mar 01 21:59:49 GMT 2022 Richard Henderson <richard.henderson@linaro.org> target/arm: Implement FEAT_LVA
This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size).
Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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