Searched hist:"84 fcf3c1" (Results 1 – 9 of 9) sorted by relevance
/qemu/hw/riscv/ |
H A D | meson.build | 84fcf3c1 Thu Sep 03 10:40:17 GMT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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H A D | Kconfig | 84fcf3c1 Thu Sep 03 10:40:17 GMT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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H A D | sifive_e.c | 84fcf3c1 Thu Sep 03 10:40:17 GMT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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H A D | microchip_pfsoc.c | 84fcf3c1 Thu Sep 03 10:40:17 GMT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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H A D | sifive_u.c | 84fcf3c1 Thu Sep 03 10:40:17 GMT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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H A D | virt.c | 84fcf3c1 Thu Sep 03 10:40:17 GMT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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/qemu/hw/intc/ |
H A D | Kconfig | 84fcf3c1 Thu Sep 03 10:40:17 GMT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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H A D | sifive_plic.c | 84fcf3c1 Thu Sep 03 10:40:17 GMT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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H A D | meson.build | 84fcf3c1 Thu Sep 03 10:40:17 GMT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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