/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/ |
H A D | fcopysign.ll | 16 ; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] 20 ; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] 29 ; 64: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] 32 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] 49 ; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] 53 ; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Mips/ |
H A D | fcopysign.ll | 16 ; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] 20 ; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] 29 ; 64: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] 32 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] 49 ; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] 53 ; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/ |
H A D | fcopysign.ll | 16 ; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] 20 ; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] 29 ; 64: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] 32 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] 49 ; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] 53 ; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 99 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 119 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 139 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 159 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 210 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 239 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 266 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 296 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 328 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 355 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 99 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 119 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 139 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 159 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 210 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 239 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 266 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 296 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 328 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 355 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 99 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 119 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 139 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 159 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 210 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 239 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 266 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 296 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 328 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 355 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-and.mir | 100 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 120 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 140 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 160 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 211 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 240 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 267 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 297 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 329 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] 356 ; CHECK: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]] [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/GlobalISel/ |
H A D | legalize-reduce-and.mir | 47 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] 48 ; CHECK-NEXT: $w0 = COPY [[AND1]](s32) 79 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]] 119 ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]] 176 ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]] 242 ; CHECK-NEXT: $w0 = COPY [[AND1]](s32) 276 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]] 314 ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]] 558 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND1]](s32) 642 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[UV1]] [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/InstCombine/ |
H A D | out-of-bounds-indexes.ll | 8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3 10 ; CHECK-NEXT: ret i32 [[AND1]] 22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3 24 ; CHECK-NEXT: ret i128 [[AND1]]
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/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/InstCombine/ |
H A D | out-of-bounds-indexes.ll | 8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3 10 ; CHECK-NEXT: ret i32 [[AND1]] 22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3 24 ; CHECK-NEXT: ret i128 [[AND1]]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/InstCombine/ |
H A D | out-of-bounds-indexes.ll | 8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3 10 ; CHECK-NEXT: ret i32 [[AND1]] 22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3 24 ; CHECK-NEXT: ret i128 [[AND1]]
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/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/InstCombine/ |
H A D | out-of-bounds-indexes.ll | 8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3 10 ; CHECK-NEXT: ret i32 [[AND1]] 22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3 24 ; CHECK-NEXT: ret i128 [[AND1]]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/InstCombine/ |
H A D | out-of-bounds-indexes.ll | 8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3 10 ; CHECK-NEXT: ret i32 [[AND1]] 22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3 24 ; CHECK-NEXT: ret i128 [[AND1]]
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/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/InstCombine/ |
H A D | out-of-bounds-indexes.ll | 8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3 10 ; CHECK-NEXT: ret i32 [[AND1]] 22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3 24 ; CHECK-NEXT: ret i128 [[AND1]]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/InstCombine/ |
H A D | out-of-bounds-indexes.ll | 8 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[A:%.*]], 3 10 ; CHECK-NEXT: ret i32 [[AND1]] 22 ; CHECK-NEXT: [[AND1:%.*]] = and i128 [[A:%.*]], 3 24 ; CHECK-NEXT: ret i128 [[AND1]]
|