/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan91xDxe/ |
H A D | Lan91xDxeHw.h | 78 #define TCR_FORCOL BIT2 93 #define EPHSR_MULCOL BIT2 108 #define RCR_ALMUL BIT2 119 #define RPCR_LS0B BIT2 140 #define CTR_EEPROM_SEL BIT2 186 #define IST_TX_EMPTY BIT2 195 #define MGMT_MCLK BIT2 258 #define PHYSTS_LINK_STS BIT2 // Link Status
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsScs.h | 66 #define B_PCH_SCS_DEV_PG_CONFIG_PGE BIT2 ///< PG Enable 80 #define B_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD_EN_MASK (BIT2 | BIT3) 103 #define B_PCH_SCS_DEV_MEM_SWRST_DATALINE BIT2 123 #define B_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_MASK (BIT0 | BIT1 | BIT2) 171 #define B_PCH_PCR_SCS_IOSFCTL_MAX_RD_PEND (BIT3 | BIT2 | BIT1 | BIT0) ///< Max upstream p… 192 #define B_PCH_PCR_SCS_GPPRVRW2_SDIO_SDCARD_DIS BIT2 ///< 1: SDIO Host C…
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H A D | PchRegsLan.h | 51 #define B_PCH_LAN_PMC_VS (BIT2 | BIT1 | BIT0) 73 #define B_PCH_LAN_MCTL_MMC (BIT3 | BIT2 | BIT1) 97 #define B_PCH_LAN_CPCE_D3HE BIT2 102 #define B_PCH_LAN_CD0I3_D0I3 BIT2 130 #define B_PCH_LAN_CSR_PHY_CTRL_LPLUND BIT2
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H A D | PchRegsHda.h | 97 #define B_PCH_HDABA_WAKEEN_SDI_2 BIT2 103 #define B_PCH_HDABA_WAKESTS_SDIN2 BIT2 147 #define B_PCH_HDABA_PCE_D3HE BIT2 168 #define B_PCH_PCR_HDA_FNCFG_ADSPD BIT2 171 #define B_PCH_PCR_HDA_CDCCFG_DIS_SDIN2 BIT2
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
H A D | PchRegsSmbus.h | 62 #define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0' 83 #define B_PCH_SMBUS_DERR BIT2 // Device Error 131 #define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported 137 #define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control 145 #define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
H A D | PchRegsSmbus.h | 56 #define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0' 77 #define B_PCH_SMBUS_DERR BIT2 // Device Error 125 #define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported 131 #define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control 139 #define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/ |
H A D | PmcRegs.h | 83 #define B_ACPI_IO_SMI_EN_BIOS BIT2 106 #define B_ACPI_IO_SMI_STS_BIOS BIT2 142 #define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2 155 #define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2 170 #define B_TCO_IO_TCO1_STS_TCO_INT BIT2 222 #define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2 246 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0)
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/dports/mail/spambnc/usr/local/sb/functions/ |
H A D | cidrmatch.rc | 116 BIT2=4 126 { BIT2=0 } 219 * $ ${BIT2}^0 234 * $ ${BIT2}^0 344 BIT2=4 354 { BIT2=0 } 444 * $ ${BIT2}^0 459 * $ ${BIT2}^0 569 BIT2=4 579 { BIT2=0 } [all …]
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/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
H A D | Isp1761UsbDxe.h | 38 #define ISP1761_DC_INTERRUPT_PSOF BIT2 59 #define ISP1761_MODE_WKUPCS BIT2 69 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6 76 #define ISP1761_CTRL_FUNCTION_DSEN BIT2 92 #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
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/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
H A D | Isp1761UsbDxe.h | 38 #define ISP1761_DC_INTERRUPT_PSOF BIT2 59 #define ISP1761_MODE_WKUPCS BIT2 69 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6 76 #define ISP1761_CTRL_FUNCTION_DSEN BIT2 92 #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
H A D | Isp1761UsbDxe.h | 44 #define ISP1761_DC_INTERRUPT_PSOF BIT2 65 #define ISP1761_MODE_WKUPCS BIT2 75 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6 82 #define ISP1761_CTRL_FUNCTION_DSEN BIT2 98 #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
H A D | Isp1761UsbDxe.h | 38 #define ISP1761_DC_INTERRUPT_PSOF BIT2 59 #define ISP1761_MODE_WKUPCS BIT2 69 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6 76 #define ISP1761_CTRL_FUNCTION_DSEN BIT2 92 #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
H A D | Isp1761UsbDxe.h | 38 #define ISP1761_DC_INTERRUPT_PSOF BIT2 59 #define ISP1761_MODE_WKUPCS BIT2 69 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6 76 #define ISP1761_CTRL_FUNCTION_DSEN BIT2 92 #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Isp1761UsbDxe/ |
H A D | Isp1761UsbDxe.h | 45 #define ISP1761_DC_INTERRUPT_PSOF BIT2 66 #define ISP1761_MODE_WKUPCS BIT2 76 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6 83 #define ISP1761_CTRL_FUNCTION_DSEN BIT2 99 #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/scsi/ |
H A D | dc395x.h | 74 #define BIT2 0x00000004 macro 81 #define FORMATING_MEDIA BIT2 87 #define ASPI_SUPPORT BIT2 123 #define RESET_DONE BIT2 131 #define OVER_RUN BIT2 141 #define RESET_DEV0 BIT2 167 #define WIDE_NEGO_ENABLE BIT2 594 #define RST_SCSI_BUS BIT2
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/scsi/ |
H A D | dc395x.h | 74 #define BIT2 0x00000004 macro 81 #define FORMATING_MEDIA BIT2 87 #define ASPI_SUPPORT BIT2 123 #define RESET_DONE BIT2 131 #define OVER_RUN BIT2 141 #define RESET_DEV0 BIT2 167 #define WIDE_NEGO_ENABLE BIT2 594 #define RST_SCSI_BUS BIT2
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/EmbeddedPkg/Drivers/Lan9118Dxe/ |
H A D | Lan9118DxeHw.h | 63 #define RXSTATUS_DB BIT2 // Dribbling bit: Frame had… 80 #define TXSTATUS_EDEF BIT2 // Tx ended because of exce… 131 #define HWCFG_BMODE BIT2 // 32/16 bit Mode bit … 138 #define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals 160 #define PHYSTS_LINK_STS BIT2 // Link Status 200 #define MACCR_RX_EN BIT2 // Enable Receiver bit 221 #define WUCSR_WUEN BIT2 // Allow remote wake up using Wa… 236 #define TXCFG_TXSAO BIT2 // Tx Status FIFO full
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/scsi/ |
H A D | dc395x.h | 74 #define BIT2 0x00000004 macro 81 #define FORMATING_MEDIA BIT2 87 #define ASPI_SUPPORT BIT2 123 #define RESET_DONE BIT2 131 #define OVER_RUN BIT2 141 #define RESET_DEV0 BIT2 167 #define WIDE_NEGO_ENABLE BIT2 594 #define RST_SCSI_BUS BIT2
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/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/fw/fet/EnergyTrace_TSPA/ |
H A D | VCC_Current.c | 366 if (i2cData & BIT2) { P2DIR |= BIT7; } in calibrationSetLoad() 386 if (i2cData & BIT2) { P2OUT |= BIT7; } in calibrationSetLoad() 477 P1SEL |= BIT2; // DCDC_PULSE = TA0.1 output in main() 479 P1DIR = BIT1+BIT2+BIT3; // DCDC_PULSE, DCDC_IO0 are output in main() 487 P2DIR = BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7; in main() 501 P1SEL |= BIT2; // DCDC_PULSE = TA0.1 output in main() 503 P1DIR = BIT2+BIT3; // DCDC_PULSE, DCDC_IO0, DCDC_IO1 are output in main() 513 P2DIR = BIT0+BIT1+BIT2+BIT3+BIT4+BIT5; in main()
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsHda.h | 107 #define B_HDA_MEM_WAKEEN_SDI_2 BIT2 113 #define B_HDA_MEM_WAKESTS_SDIN2 BIT2 157 #define B_HDA_MEM_PCE_D3HE BIT2 178 #define B_HDA_PCR_FNCFG_ADSPD BIT2 181 #define B_HDA_PCR_CDCCFG_DIS_SDIN2 BIT2
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/Include/ |
H A D | QuarkNcSocId.h | 232 #define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN 325 #define B_CFG_STICKY_RW_IMR_VIOLATION BIT2 390 #define B_QNC_SMBUS_BERR (BIT2) // BUS Error 490 #define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep 505 #define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep 539 #define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0) 561 #define B_QNC_LPC_BIOS_CNTL_BCD (BIT2) 647 #define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable 677 #define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Er… 719 #define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status [all …]
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkSouthCluster/Include/ |
H A D | I2cRegs.h | 44 #define B_I2C_REG_CON_SPEED (BIT2+BIT1) // standard mode (01) or fast mode (10) 47 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) //… 82 #define B_I2C_REG_TXFLR (BIT3+BIT2+BIT1+BIT0) // Transmit FIFO Level Register … 84 #define B_I2C_REG_RXFLR (BIT3+BIT2+BIT1+BIT0) // Receive FIFO Level Register b…
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8192e/rtl8192e/ |
H A D | r8192E_hw.h | 130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \ 147 #define RCR_AM BIT2 203 #define SCR_TxEncEnable BIT2 226 #define IMR_VIDOK BIT2 233 #define TPPoll_VIQ BIT2 273 #define AcmHw_ViqEn BIT2 281 #define AcmFw_VoqStatus BIT2 334 #define BW_OPMODE_20MHZ BIT2 363 #define RRSR_5_5M BIT2
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8192e/rtl8192e/ |
H A D | r8192E_hw.h | 130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \ 147 #define RCR_AM BIT2 203 #define SCR_TxEncEnable BIT2 226 #define IMR_VIDOK BIT2 233 #define TPPoll_VIQ BIT2 273 #define AcmHw_ViqEn BIT2 281 #define AcmFw_VoqStatus BIT2 334 #define BW_OPMODE_20MHZ BIT2 363 #define RRSR_5_5M BIT2
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8192e/rtl8192e/ |
H A D | r8192E_hw.h | 130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \ 147 #define RCR_AM BIT2 203 #define SCR_TxEncEnable BIT2 226 #define IMR_VIDOK BIT2 233 #define TPPoll_VIQ BIT2 273 #define AcmHw_ViqEn BIT2 281 #define AcmFw_VoqStatus BIT2 334 #define BW_OPMODE_20MHZ BIT2 363 #define RRSR_5_5M BIT2
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