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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Include/
H A DPcieRegs.h69 #define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type
91 #define B_PCIE_DSTS_APD BIT4 ///< AUX Power Detected
118 #define B_PCIE_LCTL_LD BIT4 ///< Link Disable
176 #define B_PCIE_DCTL2_CTD BIT4 ///< Completion Timeout Disable
193 #define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization Phase 3 Successful
296 #define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates supported
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/
H A DPchRegsPcie.h167 #define B_PCH_PCIE_MPC2_ASPMCOEN BIT4
208 #define B_PCH_PCIE_RPDCGEN_BBCLKREQEN BIT4
227 #define B_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4)
250 #define B_PCH_PCIE_STRPFUSECFG_LTCGDIS BIT4
292 #define B_PCH_PCIE_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4)
321 #define B_PCH_PCIE_PCIEDBG_LR BIT4
360 #define B_PCH_PCIE_PCIEPMECTL2_L1SCPGE BIT4
484 #define B_PCH_PCR_SPX_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port 2 Function Numb…
501 #define B_PCH_PCR_SPX_PCIEHBP_PCIERIL0O BIT4 ///< PCIe receiver-in-L0 …
H A DPchRegsPmc.h70 #define B_PCH_PMC_GEN_PMCON_A_SMI_LOCK BIT4
135 #define B_PCH_ACPI_PM1_STS_BM BIT4
188 #define B_PCH_SMI_EN_ON_SLP_EN BIT4
231 #define B_PCH_SMI_STS_ON_SLP_EN BIT4
374 #define B_PCH_TCO2_STS_SMLINK_SLV_SMI BIT4
414 #define B_PCH_PWRM_PRSTS_FIELD_1 BIT4
507 #define B_PCH_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4)
570 #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< SerialIo Controller I2C Devi…
589 #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCIe Controller A Port 2 Fun…
611 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A2_FUSE_DIS BIT4 ///< PCIe Controller A Port 2 Fus…
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/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdePkg/Include/IndustryStandard/
H A DSpdm.h103 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)
105 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4
133 #define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4
146 #define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4
175 #define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdePkg/Include/IndustryStandard/
H A DSpdm.h103 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)
105 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4
133 #define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4
146 #define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4
175 #define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdePkg/Include/IndustryStandard/
H A DSpdm.h103 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)
105 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4
133 #define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4
146 #define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4
175 #define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdePkg/Include/IndustryStandard/
H A DSpdm.h103 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)
105 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4
133 #define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4
146 #define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4
175 #define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsSata.h73 #define B_PCH_SATA_COMMAND_PMWE BIT4 // Memory Write and Invalidate Enable
87 #define B_PCH_SATA_PCISTS_CAP_LIST BIT4 // Capabilities List
133 #define B_PCH_SATA_LBAR_BA4 BIT4 // Base Address 4
195 #define B_PCH_SATA_PCS_PORT4_EN BIT4 // Port 4 Enabled
204 #define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 // Port 4 Implemented
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdePkg/Include/IndustryStandard/
H A DSpdm.h103 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)
105 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4
133 #define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4
146 #define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4
175 #define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4
/dports/sysutils/edk2/edk2-edk2-stable202102/MdePkg/Include/IndustryStandard/
H A DSpdm.h103 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)
105 #define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4
133 #define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4
146 #define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4
175 #define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsSata.h67 #define B_PCH_SATA_COMMAND_PMWE BIT4 // Memory Write and Invalidate Enable
81 #define B_PCH_SATA_PCISTS_CAP_LIST BIT4 // Capabilities List
127 #define B_PCH_SATA_LBAR_BA4 BIT4 // Base Address 4
189 #define B_PCH_SATA_PCS_PORT4_EN BIT4 // Port 4 Enabled
198 #define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 // Port 4 Implemented
/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
68 #define USBCMD_FGR BIT4 // Force Global Resume
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
86 #define USBTD_BABBLE BIT4 // Babble condition
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h53 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
74 #define USBCMD_FGR BIT4 // Force Global Resume
86 #define USBSTS_HCPE BIT4 // Host Controller Process Error
92 #define USBTD_BABBLE BIT4 // Babble condition
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
68 #define USBCMD_FGR BIT4 // Force Global Resume
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
86 #define USBTD_BABBLE BIT4 // Babble condition
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
68 #define USBCMD_FGR BIT4 // Force Global Resume
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
86 #define USBTD_BABBLE BIT4 // Babble condition
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
68 #define USBCMD_FGR BIT4 // Force Global Resume
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
86 #define USBTD_BABBLE BIT4 // Babble condition
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
68 #define USBCMD_FGR BIT4 // Force Global Resume
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
86 #define USBTD_BABBLE BIT4 // Babble condition
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
68 #define USBCMD_FGR BIT4 // Force Global Resume
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
86 #define USBTD_BABBLE BIT4 // Babble condition
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
68 #define USBCMD_FGR BIT4 // Force Global Resume
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
86 #define USBTD_BABBLE BIT4 // Babble condition
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
68 #define USBCMD_FGR BIT4 // Force Global Resume
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
86 #define USBTD_BABBLE BIT4 // Babble condition
/dports/sysutils/edk2/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/UhciDxe/
H A DUhciReg.h47 #define USBPORTSC_LSL BIT4 // Line Status Low BIT
68 #define USBCMD_FGR BIT4 // Force Global Resume
80 #define USBSTS_HCPE BIT4 // Host Controller Process Error
86 #define USBTD_BABBLE BIT4 // Babble condition
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/
H A DPchRegsFia.h60 #define B_PCH_FIA_PCR_L1O (BIT7 | BIT6 | BIT5 | BIT4)
68 #define B_PCH_FIA_PCR_L9O (BIT7 | BIT6 | BIT5 | BIT4)
76 #define B_PCH_FIA_PCR_L17O (BIT7 | BIT6 | BIT5 | BIT4)
84 #define B_PCH_FIA_PCR_L25O (BIT7 | BIT6 | BIT5 | BIT4)
H A DPchRegsPmc.h61 #define B_ACPI_IO_PM1_STS_BM BIT4
112 #define B_ACPI_IO_SMI_EN_ON_SLP_EN BIT4
155 #define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4
299 #define B_TCO_IO_TCO2_STS_SMLINK_SLV_SMI BIT4
400 #define B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4
447 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_B0 BIT4
456 #define B_PMC_PWRM_PRSTS_FIELD_1 BIT4
559 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4)
595 #define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< SerialIo Controller I2C Devi…
632 #define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCIe Controller A Port 2 Fu…
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/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/hil/msp_fet/
H A DhilAdcControl.c106 P6OUT &= ~(BIT1+BIT3+BIT4+BIT6); in hil_AdcControlInitADC()
107 P6SEL |= (BIT1+BIT3+BIT4+BIT6); in hil_AdcControlInitADC()
151 P6OUT &= ~(BIT0+BIT1+BIT4+BIT6); in hil_AdcControlInitADCvFuse()
152 P6SEL |= BIT0+BIT1+BIT4+BIT6; in hil_AdcControlInitADCvFuse()
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/
H A DPchRegsPmc.h71 #define B_PCH_PMC_GEN_PMCON_A_SMI_LOCK BIT4
136 #define B_PCH_ACPI_PM1_STS_BM BIT4
189 #define B_PCH_SMI_EN_ON_SLP_EN BIT4
232 #define B_PCH_SMI_STS_ON_SLP_EN BIT4
375 #define B_PCH_TCO2_STS_SMLINK_SLV_SMI BIT4
415 #define B_PCH_PWRM_PRSTS_FIELD_1 BIT4
508 #define B_PCH_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4)
571 #define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< SerialIo Controller I2C Devi…
590 #define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCIe Controller A Port 2 Fun…
612 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A2_FUSE_DIS BIT4 ///< PCIe Controller A Port 2 Fus…
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