/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | inst-select-pattern-and-or.mir | 20 ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 22 ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 28 ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 30 ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 54 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 62 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 87 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 95 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 120 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 123 ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec [all …]
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H A D | regbankselect-fshr.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-fshr.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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H A D | inst-select-pattern-and-or.mir | 20 ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 22 ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 28 ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 30 ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 54 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 62 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 87 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 95 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 120 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 123 ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec [all …]
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H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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H A D | regbankselect-fshr.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-fshr.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | inst-select-pattern-and-or.mir | 20 ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 22 ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 28 ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 30 ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 54 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 62 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 87 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 95 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 120 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 123 ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec [all …]
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H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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H A D | regbankselect-fshr.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | inst-select-pattern-and-or.mir | 20 ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 22 ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 28 ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 30 ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 54 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 62 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 87 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 95 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 120 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 123 ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec [all …]
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H A D | regbankselect-fshr.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-fshr.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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H A D | inst-select-pattern-and-or.mir | 20 ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 22 ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 28 ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 30 ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 54 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 62 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 87 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 95 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 120 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 123 ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec [all …]
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H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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H A D | regbankselect-fshr.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 17 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 34 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 36 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 53 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 54 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 71 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 89 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 107 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 125 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | inst-select-pattern-and-or.mir | 20 ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 22 ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 28 ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 30 ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc 54 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 62 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 87 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 95 ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 120 ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 123 ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec [all …]
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H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 18 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 35 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 37 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 54 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 56 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 73 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 92 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 110 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 128 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 17 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 34 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 36 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 53 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 54 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 71 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 89 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 107 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 125 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | regbankselect-fma.mir | 15 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 17 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 34 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 36 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 53 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 54 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 71 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 89 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 107 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 125 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 [all …]
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