1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
3# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
4# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
5
6---
7
8name:            and_or_s32_sgpr_sgpr_sgpr
9legalized:       true
10regBankSelected: true
11tracksRegLiveness: true
12
13body: |
14  bb.0:
15    liveins: $sgpr0, $sgpr1, $sgpr2
16    ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
17    ; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
18    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
20    ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
21    ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
22    ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
23    ; GFX8: S_ENDPGM 0, implicit [[S_OR_B32_]]
24    ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
25    ; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
26    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
27    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
28    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
29    ; GFX9: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
30    ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
31    ; GFX9: S_ENDPGM 0, implicit [[S_OR_B32_]]
32    %0:sgpr(s32) = COPY $sgpr0
33    %1:sgpr(s32) = COPY $sgpr1
34    %2:sgpr(s32) = COPY $sgpr2
35    %3:sgpr(s32) = G_AND %0, %1
36    %4:sgpr(s32) = G_OR %3, %2
37    S_ENDPGM 0, implicit %4
38...
39
40---
41
42name:            and_or_s32_vgpr_vgpr_vgpr
43legalized:       true
44regBankSelected: true
45tracksRegLiveness: true
46
47body: |
48  bb.0:
49    liveins: $vgpr0, $vgpr1, $vgpr2
50    ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
51    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
52    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
53    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
54    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
55    ; GFX8: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
56    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_AND_B32_e64_]], [[COPY2]], implicit $exec
57    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
58    ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
59    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
60    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
61    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
62    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
63    ; GFX9: [[V_AND_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
64    ; GFX9: S_ENDPGM 0, implicit [[V_AND_OR_B32_e64_]]
65    %0:vgpr(s32) = COPY $vgpr0
66    %1:vgpr(s32) = COPY $vgpr1
67    %2:vgpr(s32) = COPY $vgpr2
68    %3:vgpr(s32) = G_AND %0, %1
69    %4:vgpr(s32) = G_OR %3, %2
70    S_ENDPGM 0, implicit %4
71...
72
73---
74
75name:            and_or_s32_vgpr_vgpr_vgpr_commute
76legalized:       true
77regBankSelected: true
78tracksRegLiveness: true
79
80body: |
81  bb.0:
82    liveins: $vgpr0, $vgpr1, $vgpr2
83    ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
84    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
85    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
86    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
87    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
88    ; GFX8: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
89    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY2]], [[V_AND_B32_e64_]], implicit $exec
90    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
91    ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
92    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
93    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
94    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
95    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
96    ; GFX9: [[V_AND_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
97    ; GFX9: S_ENDPGM 0, implicit [[V_AND_OR_B32_e64_]]
98    %0:vgpr(s32) = COPY $vgpr0
99    %1:vgpr(s32) = COPY $vgpr1
100    %2:vgpr(s32) = COPY $vgpr2
101    %3:vgpr(s32) = G_AND %0, %1
102    %4:vgpr(s32) = G_OR %2, %3
103    S_ENDPGM 0, implicit %4
104...
105
106---
107
108name:            and_or_s32_sgpr_sgpr_vgpr
109legalized:       true
110regBankSelected: true
111tracksRegLiveness: true
112
113body: |
114  bb.0:
115    liveins: $sgpr0, $sgpr1, $vgpr0
116    ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
117    ; GFX8: liveins: $sgpr0, $sgpr1, $vgpr0
118    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
119    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
120    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
121    ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
122    ; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
123    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
124    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
125    ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
126    ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0
127    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
128    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
129    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
130    ; GFX9: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
131    ; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
132    ; GFX9: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
133    ; GFX9: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
134    %0:sgpr(s32) = COPY $sgpr0
135    %1:sgpr(s32) = COPY $sgpr1
136    %2:vgpr(s32) = COPY $vgpr0
137    %3:sgpr(s32) = G_AND %0, %1
138    %4:vgpr(s32) = COPY %3
139    %5:vgpr(s32) = G_OR %4, %2
140    S_ENDPGM 0, implicit %5
141...
142