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Searched refs:ICR (Results 26 – 50 of 825) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/sound/pcmcia/vx/
H A Dvxp_ops.c153 vx_outb(chip, ICR, 0); in vxp_load_xilinx_binary()
161 vx_outb(chip, ICR, ICR_HF1); in vxp_load_xilinx_binary()
177 vx_outb(chip, ICR, 0); in vxp_load_xilinx_binary()
193 vx_outb(chip, ICR, ICR_HF0); in vxp_load_xilinx_binary()
316 vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); in vx_setup_pseudo_dma()
341 vx_outb(chip, ICR, 0); in vx_release_pseudo_dma()
425 vx_outb(chip, ICR, 0); in vxp_dma_read()
/dports/multimedia/v4l-utils/linux-5.13-rc2/sound/pcmcia/vx/
H A Dvxp_ops.c153 vx_outb(chip, ICR, 0); in vxp_load_xilinx_binary()
161 vx_outb(chip, ICR, ICR_HF1); in vxp_load_xilinx_binary()
177 vx_outb(chip, ICR, 0); in vxp_load_xilinx_binary()
193 vx_outb(chip, ICR, ICR_HF0); in vxp_load_xilinx_binary()
316 vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); in vx_setup_pseudo_dma()
341 vx_outb(chip, ICR, 0); in vx_release_pseudo_dma()
425 vx_outb(chip, ICR, 0); in vxp_dma_read()
/dports/math/slatec/src/
H A Dsoseqs.f106 ICR = 0
342 ICR = ICR + 1
343 IF (ICR .LT. NSRRC) GO TO 270
347 260 ICR = 0
/dports/lang/micropython/micropython-1.17/ports/stm32/
H A Dsdio.c179 SDMMC->ICR = SDMMC_ICR_CMDRENDC; in SDMMC_IRQHandler()
221 SDMMC->ICR = SDMMC_ICR_DATAENDC; in SDMMC_IRQHandler()
258 SDMMC->ICR = SDMMC_ICR_SDIOITC; in SDMMC_IRQHandler()
269 SDMMC->ICR = SDMMC_STATIC_FLAGS; in SDMMC_IRQHandler()
285 SDMMC->ICR = SDMMC_STATIC_FLAGS; // clear interrupts in sdio_transfer()
358 SDMMC->ICR = SDMMC_STATIC_FLAGS; // clear interrupts in sdio_transfer_cmd53()
H A Di2cslave.c79 i2c->ICR = I2C_ICR_ADDRCF; in i2c_slave_ev_irq_handler()
90 i2c->ICR = I2C_ICR_STOPCF; in i2c_slave_ev_irq_handler()
/dports/editors/fpc-ide/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny28.pp14 ICR : byte absolute $00+$26; // Interrupt Control Register
45 // ICR
61 // ICR
73 // ICR
/dports/lang/fpc-source/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny28.pp14 ICR : byte absolute $00+$26; // Interrupt Control Register
45 // ICR
61 // ICR
73 // ICR
/dports/lang/fpc/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny28.pp14 ICR : byte absolute $00+$26; // Interrupt Control Register
45 // ICR
61 // ICR
73 // ICR
/dports/lang/fpc-utils/fpc-3.2.2/rtl/embedded/avr/
H A Dattiny28.pp14 ICR : byte absolute $00+$26; // Interrupt Control Register
45 // ICR
61 // ICR
73 // ICR
/dports/math/cmlib/cmlib-3.0_8/src/snls1e/
H A Dsoseqs.f91 ICR = 0
327 ICR = ICR + 1
328 IF (ICR .LT. NSRRC) GO TO 270
332 260 ICR = 0
/dports/editors/biew/biew-610/plugins/
H A Dtextmode.htx3 %ICR%i or/and %ILF%i characters (or after end of screen lines into wrap mode).
8 strings after %ICR%i or/and %ILF%i characters.
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/
H A Dstm32f4xx_dcmi.c130 DCMI->ICR = 0x1F; in DCMI_DeInit()
469 DCMI->ICR = DCMI_FLAG; in DCMI_ClearFlag()
520 DCMI->ICR = DCMI_IT; in DCMI_ClearITPendingBit()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F4xx_StdPeriph_Driver/src/
H A Dstm32f4xx_dcmi.c130 DCMI->ICR = 0x1F; in DCMI_DeInit()
469 DCMI->ICR = DCMI_FLAG; in DCMI_ClearFlag()
520 DCMI->ICR = DCMI_IT; in DCMI_ClearITPendingBit()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/net/
H A Dtrace-events163 e1000e_rx_written_to_guest(uint32_t causes) "Received packet written to guest (ICR causes %u)"
165 e1000e_rx_interrupt_set(uint32_t causes) "Receive interrupt set (ICR causes %u)"
166 e1000e_rx_interrupt_delayed(uint32_t causes) "Receive interrupt delayed (ICR causes %u)"
211 e1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims) "ICR PENDING: 0x%x (ICR…
213 e1000e_irq_set_cause_exit(uint32_t val, uint32_t icr) "Set IRQ cause 0x%x, ICR: 0x%x"
215 e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x"
219 e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0x%x"
220 e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x"
221 e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS"
222 e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME"
[all …]
H A De1000e_core.c364 core->mac[ICR] |= val; in e1000e_intrmgr_fire_all_timers()
2111 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2164 core->mac[ICS] = core->mac[ICR]; in e1000e_update_interrupt_state()
2195 core->mac[ICR] |= val; in e1000e_set_interrupt_cause()
2471 icr = core->mac[ICR] & ~val; in e1000e_set_icr()
2477 core->mac[ICR] = icr; in e1000e_set_icr()
2610 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2615 core->mac[ICR] = 0; in e1000e_mac_icr_read()
2621 core->mac[ICR] = 0; in e1000e_mac_icr_read()
3003 [ICR] = e1000e_mac_icr_read,
[all …]
/dports/emulators/qemu42/qemu-4.2.1/hw/net/
H A De1000e_core.c365 core->mac[ICR] |= val; in e1000e_intrmgr_fire_all_timers()
2112 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2165 core->mac[ICS] = core->mac[ICR]; in e1000e_update_interrupt_state()
2196 core->mac[ICR] |= val; in e1000e_set_interrupt_cause()
2472 icr = core->mac[ICR] & ~val; in e1000e_set_icr()
2478 core->mac[ICR] = icr; in e1000e_set_icr()
2611 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2616 core->mac[ICR] = 0; in e1000e_mac_icr_read()
2622 core->mac[ICR] = 0; in e1000e_mac_icr_read()
3004 [ICR] = e1000e_mac_icr_read,
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/net/
H A De1000e_core.c365 core->mac[ICR] |= val; in e1000e_intrmgr_fire_all_timers()
2104 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2157 core->mac[ICS] = core->mac[ICR]; in e1000e_update_interrupt_state()
2188 core->mac[ICR] |= val; in e1000e_set_interrupt_cause()
2463 icr = core->mac[ICR] & ~val; in e1000e_set_icr()
2469 core->mac[ICR] = icr; in e1000e_set_icr()
2602 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2607 core->mac[ICR] = 0; in e1000e_mac_icr_read()
2613 core->mac[ICR] = 0; in e1000e_mac_icr_read()
3002 [ICR] = e1000e_mac_icr_read,
[all …]
/dports/emulators/qemu60/qemu-6.0.0/hw/net/
H A De1000e_core.c365 core->mac[ICR] |= val; in e1000e_intrmgr_fire_all_timers()
2105 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2158 core->mac[ICS] = core->mac[ICR]; in e1000e_update_interrupt_state()
2189 core->mac[ICR] |= val; in e1000e_set_interrupt_cause()
2465 icr = core->mac[ICR] & ~val; in e1000e_set_icr()
2471 core->mac[ICR] = icr; in e1000e_set_icr()
2604 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2609 core->mac[ICR] = 0; in e1000e_mac_icr_read()
2615 core->mac[ICR] = 0; in e1000e_mac_icr_read()
3004 [ICR] = e1000e_mac_icr_read,
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/net/
H A De1000e_core.c365 core->mac[ICR] |= val; in e1000e_intrmgr_fire_all_timers()
2112 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2165 core->mac[ICS] = core->mac[ICR]; in e1000e_update_interrupt_state()
2196 core->mac[ICR] |= val; in e1000e_set_interrupt_cause()
2472 icr = core->mac[ICR] & ~val; in e1000e_set_icr()
2478 core->mac[ICR] = icr; in e1000e_set_icr()
2611 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2616 core->mac[ICR] = 0; in e1000e_mac_icr_read()
2622 core->mac[ICR] = 0; in e1000e_mac_icr_read()
3004 [ICR] = e1000e_mac_icr_read,
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/net/
H A De1000e_core.c365 core->mac[ICR] |= val; in e1000e_intrmgr_fire_all_timers()
2112 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2165 core->mac[ICS] = core->mac[ICR]; in e1000e_update_interrupt_state()
2196 core->mac[ICR] |= val; in e1000e_set_interrupt_cause()
2472 icr = core->mac[ICR] & ~val; in e1000e_set_icr()
2478 core->mac[ICR] = icr; in e1000e_set_icr()
2611 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2616 core->mac[ICR] = 0; in e1000e_mac_icr_read()
2622 core->mac[ICR] = 0; in e1000e_mac_icr_read()
3011 [ICR] = e1000e_mac_icr_read,
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/net/
H A De1000e_core.c365 core->mac[ICR] |= val; in e1000e_intrmgr_fire_all_timers()
2112 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2165 core->mac[ICS] = core->mac[ICR]; in e1000e_update_interrupt_state()
2196 core->mac[ICR] |= val; in e1000e_set_interrupt_cause()
2472 icr = core->mac[ICR] & ~val; in e1000e_set_icr()
2478 core->mac[ICR] = icr; in e1000e_set_icr()
2611 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2616 core->mac[ICR] = 0; in e1000e_mac_icr_read()
2622 core->mac[ICR] = 0; in e1000e_mac_icr_read()
3012 [ICR] = e1000e_mac_icr_read,
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/net/
H A De1000e_core.c365 core->mac[ICR] |= val;
2104 if (core->mac[ICR]) {
2157 core->mac[ICS] = core->mac[ICR];
2188 core->mac[ICR] |= val;
2463 icr = core->mac[ICR] & ~val;
2469 core->mac[ICR] = icr;
2602 uint32_t ret = core->mac[ICR];
2607 core->mac[ICR] = 0;
2613 core->mac[ICR] = 0;
3002 [ICR] = e1000e_mac_icr_read,
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/net/
H A De1000e_core.c365 core->mac[ICR] |= val; in e1000e_intrmgr_fire_all_timers()
2112 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2165 core->mac[ICS] = core->mac[ICR]; in e1000e_update_interrupt_state()
2196 core->mac[ICR] |= val; in e1000e_set_interrupt_cause()
2472 icr = core->mac[ICR] & ~val; in e1000e_set_icr()
2478 core->mac[ICR] = icr; in e1000e_set_icr()
2611 uint32_t ret = core->mac[ICR]; in e1000e_mac_icr_read()
2616 core->mac[ICR] = 0; in e1000e_mac_icr_read()
2622 core->mac[ICR] = 0; in e1000e_mac_icr_read()
3008 [ICR] = e1000e_mac_icr_read,
[all …]
/dports/emulators/qemu5/qemu-5.2.0/target/tricore/
H A Dgdbstub.c52 return env->ICR; in tricore_cpu_gdb_read_csfr()
90 env->ICR = val; in tricore_cpu_gdb_write_csfr()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/tricore/
H A Dgdbstub.c52 return env->ICR; in tricore_cpu_gdb_read_csfr()
90 env->ICR = val; in tricore_cpu_gdb_write_csfr()

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