/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.td | 40 // SPR - One of the 32-bit special-purpose registers 41 class SPR<bits<10> num, string n> : PPCReg<n> { 250 def LR : SPR<8, "lr">, DwarfRegNum<[65]>; 252 def LR8 : SPR<8, "lr">, DwarfRegNum<[65]>; 255 def CTR : SPR<9, "ctr">, DwarfRegNum<[66]>; 256 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>; 259 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[107]>; 262 // (which really is SPR register 1); this is the only bit interesting to a 264 def CARRY: SPR<1, "ca">, DwarfRegNum<[0]>; 273 // Also, in the architecture it is not really a SPR; 512 is arbitrary. [all …]
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H A D | PPCInstrFormats.td | 498 bits<10> SPR; 501 let Inst{11} = SPR{4}; 502 let Inst{12} = SPR{3}; 503 let Inst{13} = SPR{2}; 504 let Inst{14} = SPR{1}; 505 let Inst{15} = SPR{0}; 506 let Inst{16} = SPR{9}; 507 let Inst{17} = SPR{8}; 508 let Inst{18} = SPR{7}; 518 let SPR = spr; [all …]
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/dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1319/ |
H A D | ent.vhdl | 16 -- SPR numbers 25 -- Extended GPR indice (can hold an SPR)
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H A D | repro.vhdl | 16 -- SPR numbers 25 -- Extended GPR indice (can hold an SPR)
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/dports/math/cocoalib/CoCoALib-0.99712/src/tests/ |
H A D | test-RingAssign1.C | 86 SparsePolyRing SPR = SPR1; in program() local 87 SPR = SPR2; in program()
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/dports/math/giacxcas/CoCoALib-0.99700/src/tests/ |
H A D | test-RingAssign1.C | 86 SparsePolyRing SPR = SPR1; in program() local 87 SPR = SPR2; in program()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.td | 51 // SPR - One of the 32-bit special-purpose registers 52 class SPR<bits<10> num, string n> : PPCReg<n> { 247 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 249 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 252 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 253 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 256 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 262 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 264 def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 267 // (which really is SPR register 1); this is the only bit interesting to a [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/skiboot/doc/opal-api/ |
H A D | opal-slw-set-reg-100.rst | 9 given value of SPR when there is a state loss. The actual set of SPR
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/dports/biology/sigviewer/sigviewer-0.6.4-13-gf62f8d9/src/base/ |
H A D | signal_channel.cpp | 31 samplerate_ = hdr->SampleRate * hdr->CHANNEL[ch].SPR / hdr->SPR; in SignalChannel()
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/dports/biology/biosig/biosig-2.3.3/biosig4matlab/t200_FileAccess/ |
H A D | scpopen.m | 112 HDR.NS = 0; HDR.SPR = 0; HDR.NRec = 0; HDR.Calib = zeros(1,0); 336 HDR.AS.SPR = HDR.LeadPos(:,2)-HDR.LeadPos(:,1)+1; 337 HDR.SPR = HDR.AS.SPR(1); 339 HDR.SPR = lcm(HDR.SPR,HDR.AS.SPR(k)); 389 SCP.SPR = fread(fid,HDR.NS,'uint16'); 397 outlen = HDR.SPR; 406 if any(SCP.SPR(1)~=SCP.SPR), 542 while c <= 32, %1:HDR.SPR(k), 820 HDR.SPR = size(HDR.data,1); 822 HDR.AS.endpos = HDR.SPR; [all …]
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H A D | bkropen.m | 56 BKR.SPR = fread(fid,1,'uint32'); % 4 Byte 10 Anzahl Samples per Trial 166 if (BKR.FILE.size-BKR.HeadLen)~=BKR.SPR*BKR.NRec*BKR.NS*2, 167 %[BKR.FILE.size,BKR.HeadLen,BKR.SPR,BKR.NRec,BKR.NS], 168 %[BKR.FILE.size-BKR.HeadLen-BKR.SPR*BKR.NRec*BKR.NS*2], 172 BKR.SPR=(BKR.FILE.size-BKR.HeadLen)/(BKR.NRec*BKR.NS*2); 175 BKR.NRec=(BKR.FILE.size-BKR.HeadLen)/(BKR.SPR*BKR.NS*2); 177 if (BKR.FILE.size-BKR.HeadLen)~=BKR.SPR*BKR.NRec*BKR.NS*2, 344 if ~isfield(BKR,'SPR'), 345 BKR.SPR = 0; % Unknown - Value will be fixed when file is closed. 359 …if any([BKR.NS==0,BKR.SPR==0,BKR.NRec<0,isnan([BKR.NRec,BKR.NS,BKR.SPR,BKR.DigMax,BKR.PhysMax,BKR.… [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.td | 51 // SPR - One of the 32-bit special-purpose registers 52 class SPR<bits<10> num, string n> : PPCReg<n> { 247 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 249 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 252 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 253 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 256 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 262 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 264 def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 267 // (which really is SPR register 1); this is the only bit interesting to a [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.td | 51 // SPR - One of the 32-bit special-purpose registers 52 class SPR<bits<10> num, string n> : PPCReg<n> { 247 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 249 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 252 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 253 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 256 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 262 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 264 def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 267 // (which really is SPR register 1); this is the only bit interesting to a [all …]
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/dports/biology/biosig/biosig-2.3.3/biosig4c++/t210/ |
H A D | sopen_abf_read.c | 59 hdr->SPR = 1; in sopen_atf_read() 157 hc->SPR = 1; in sopen_atf_read() 211 hdr->SPR = ln; in sopen_atf_read() 230 size_t idx = traceList[nc] * hdr->SPR + chanList[nc]*hdr->SPR*hdr->NRec + nr; in sopen_atf_read() 235 hdr->NRec *= hdr->SPR; in sopen_atf_read() 236 hdr->SPR = 1; in sopen_atf_read() 398 hdr->SPR = 1; in sopen_abf_read() 429 hc->SPR = hdr->SPR; in sopen_abf_read() 516 hc->SPR = hdr->SPR; in sopen_abf_read() 620 hdr->SPR = 1; in sopen_abf2_read() [all …]
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H A D | sopen_dcmtk_read.cpp | 243 hdr->SPR = 1; in sopen_dcmtk_read() 249 hc->SPR = hdr->SPR; in sopen_dcmtk_read() 302 bi += hc->SPR * GDFTYP_BITS[hc->GDFTYP] >> 3; in sopen_dcmtk_read()
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/dports/lang/erlang-runtime23/otp-OTP-23.3.4.10/lib/hipe/ppc/ |
H A D | hipe_ppc_pp.erl | 107 #mfspr{dst=Dst, spr=SPR} -> 108 io:format(Dev, "\tmf~w ", [spr_name(SPR)]), 115 #mtspr{spr=SPR, src=Src} -> 116 io:format(Dev, "\tmt~w ", [spr_name(SPR)]), 281 spr_name(SPR) -> SPR.
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/dports/lang/erlang-runtime22/otp-OTP-22.3.4.24/lib/hipe/ppc/ |
H A D | hipe_ppc_pp.erl | 107 #mfspr{dst=Dst, spr=SPR} -> 108 io:format(Dev, "\tmf~w ", [spr_name(SPR)]), 115 #mtspr{spr=SPR, src=Src} -> 116 io:format(Dev, "\tmt~w ", [spr_name(SPR)]), 281 spr_name(SPR) -> SPR.
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/dports/lang/erlang-runtime21/otp-OTP-21.3.8.24/lib/hipe/ppc/ |
H A D | hipe_ppc_pp.erl | 107 #mfspr{dst=Dst, spr=SPR} -> 108 io:format(Dev, "\tmf~w ", [spr_name(SPR)]), 115 #mtspr{spr=SPR, src=Src} -> 116 io:format(Dev, "\tmt~w ", [spr_name(SPR)]), 281 spr_name(SPR) -> SPR.
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/dports/science/cdf/cdf33_0-dist/src/lib/ |
H A D | cdfvalidator.c | 740 struct SPRstruct SPR; in ValidateSPR() local 746 SPR_RECORD, &SPR, in ValidateSPR() 749 if (SPR.RecordType != SPR_) in ValidateSPR() 751 4, 1, &(SPR.RecordType), 0, debug); in ValidateSPR() 752 if (SPR.RecordSize != (SPR_BASE_SIZE + SPR.pCount * sizeof(Int32))) in ValidateSPR() 754 4, 1, &(SPR.RecordSize), 0, debug); in ValidateSPR() 755 if (SPR.pCount < 1 || SPR.pCount > CDF_MAX_PARMS) in ValidateSPR() 757 4, 1, &(SPR.pCount), 0, debug); in ValidateSPR()
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H A D | cdfvalidator64.c | 780 struct SPRstruct64 SPR; in ValidateSPR() local 791 SPR_RECORD, &SPR, in ValidateSPR() 794 if (SPR.RecordType != SPR_) in ValidateSPR() 796 4, 1, &(SPR.RecordType), 0, debug); in ValidateSPR() 797 if (SPR.RecordSize != (SPR_BASE_SIZE64 + SPR.pCount * sizeof(Int32))) in ValidateSPR() 799 8, 1, &(SPR.RecordSize), 0, debug); in ValidateSPR() 800 if (SPR.pCount < 1 || SPR.pCount > CDF_MAX_PARMS) in ValidateSPR() 802 4, 1, &(SPR.pCount), 0, debug); in ValidateSPR()
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/dports/biology/biosig/biosig-2.3.3/biosig4matlab/demo/ |
H A D | demo3.m | 76 HDR.SPR = 10000; 77 HDR.Dur = HDR.SPR/HDR.SampleRate; 80 HDR.AS.SPR = [1000;100;200;100;20;0]; % samples per block; 0 indicates a channel with sparse sampli… 128 … following sparse samples are not valid because channel 5 is not defined as sparse (see HDR.AS.SPR)
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.td | 53 // SPR - One of the 32-bit special-purpose registers 54 class SPR<bits<10> num, string n> : PPCReg<n> { 263 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 265 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 268 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 269 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 272 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>; 278 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; 280 def XER: SPR<1, "xer">, DwarfRegNum<[76]>; 283 // (which really is SPR register 1); this is the only bit interesting to a [all …]
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/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/ARM/ |
H A D | ARMRegisterInfo-digit.td | 298 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 299 let AltOrders = [(add (decimate SPR, 2), SPR), 300 (add (decimate SPR, 4), 301 (decimate SPR, 2), 302 (decimate (rotl SPR, 1), 4), 303 (decimate (rotl SPR, 1), 2))]; 311 let AltOrders = [(add (decimate HPR, 2), SPR), 322 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 345 // 32-bit SPR subregs). 367 // Subset of QPR that have 32-bit SPR subregs.
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H A D | ARMRegisterInfo.td | 298 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 299 let AltOrders = [(add (decimate SPR, 2), SPR), 300 (add (decimate SPR, 4), 301 (decimate SPR, 2), 302 (decimate (rotl SPR, 1), 4), 303 (decimate (rotl SPR, 1), 2))]; 311 let AltOrders = [(add (decimate HPR, 2), SPR), 322 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 345 // 32-bit SPR subregs). 367 // Subset of QPR that have 32-bit SPR subregs.
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/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/ARM/ |
H A D | ARMRegisterInfo-digit.td | 298 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> { 299 let AltOrders = [(add (decimate SPR, 2), SPR), 300 (add (decimate SPR, 4), 301 (decimate SPR, 2), 302 (decimate (rotl SPR, 1), 4), 303 (decimate (rotl SPR, 1), 2))]; 311 let AltOrders = [(add (decimate HPR, 2), SPR), 322 // Subset of SPR which can be used as a source of NEON scalars for 16-bit 345 // 32-bit SPR subregs). 367 // Subset of QPR that have 32-bit SPR subregs.
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