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/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/ARM/
H A DARMRegisterInfo.td298 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
299 let AltOrders = [(add (decimate SPR, 2), SPR),
300 (add (decimate SPR, 4),
301 (decimate SPR, 2),
302 (decimate (rotl SPR, 1), 4),
303 (decimate (rotl SPR, 1), 2))];
311 let AltOrders = [(add (decimate HPR, 2), SPR),
322 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
345 // 32-bit SPR subregs).
367 // Subset of QPR that have 32-bit SPR subregs.
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td53 // SPR - One of the 32-bit special-purpose registers
54 class SPR<bits<10> num, string n> : PPCReg<n> {
263 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
265 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
268 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
269 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
272 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
278 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
280 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
283 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td53 // SPR - One of the 32-bit special-purpose registers
54 class SPR<bits<10> num, string n> : PPCReg<n> {
263 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
265 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
268 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
269 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
272 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
278 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
280 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
283 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td53 // SPR - One of the 32-bit special-purpose registers
54 class SPR<bits<10> num, string n> : PPCReg<n> {
263 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
265 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
268 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
269 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
272 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
278 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
280 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
283 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td53 // SPR - One of the 32-bit special-purpose registers
54 class SPR<bits<10> num, string n> : PPCReg<n> {
263 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
265 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
268 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
269 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
272 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
278 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
280 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
283 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/ARM/
H A DARMRegisterInfo.td298 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
299 let AltOrders = [(add (decimate SPR, 2), SPR),
300 (add (decimate SPR, 4),
301 (decimate SPR, 2),
302 (decimate (rotl SPR, 1), 4),
303 (decimate (rotl SPR, 1), 2))];
311 let AltOrders = [(add (decimate HPR, 2), SPR),
322 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
345 // 32-bit SPR subregs).
367 // Subset of QPR that have 32-bit SPR subregs.
H A DARMRegisterInfo-digit.td298 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
299 let AltOrders = [(add (decimate SPR, 2), SPR),
300 (add (decimate SPR, 4),
301 (decimate SPR, 2),
302 (decimate (rotl SPR, 1), 4),
303 (decimate (rotl SPR, 1), 2))];
311 let AltOrders = [(add (decimate HPR, 2), SPR),
322 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
345 // 32-bit SPR subregs).
367 // Subset of QPR that have 32-bit SPR subregs.
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td53 // SPR - One of the 32-bit special-purpose registers
54 class SPR<bits<10> num, string n> : PPCReg<n> {
263 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
265 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
268 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
269 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
272 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
278 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
280 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
283 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/biology/biosig/biosig-2.3.3/biosig4matlab/t250_ArtifactPreProcessingQualityControl/
H A Ddetect_sharp_wave_ripple.m457 H.SPR = 1;
492 H.SPR = 1;
513 H.SPR= sz(2);
534 H.AS.SPR = repmat(H.SPR,H.NS,1);
541 %H3.AS.SPR = repmat(H3.SPR,H3.NS,1);
558 H.EVENT.POS = [1:H.NRec-1]'*H.SPR+1;[1:H.NRec]';
560 %H.EVENT.POS = [HDR.EVENT.POS;[1:H.NRec]'*H.SPR-floor(H.SPR/2)];
584 H.SPR = 1;
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/
H A DARMRegisterInfo.td298 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
299 let AltOrders = [(add (decimate SPR, 2), SPR),
300 (add (decimate SPR, 4),
301 (decimate SPR, 2),
302 (decimate (rotl SPR, 1), 4),
303 (decimate (rotl SPR, 1), 2))];
311 let AltOrders = [(add (decimate HPR, 2), SPR),
322 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
345 // 32-bit SPR subregs).
367 // Subset of QPR that have 32-bit SPR subregs.
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/
H A DARMRegisterInfo.td298 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
299 let AltOrders = [(add (decimate SPR, 2), SPR),
300 (add (decimate SPR, 4),
301 (decimate SPR, 2),
302 (decimate (rotl SPR, 1), 4),
303 (decimate (rotl SPR, 1), 2))];
311 let AltOrders = [(add (decimate HPR, 2), SPR),
322 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
345 // 32-bit SPR subregs).
367 // Subset of QPR that have 32-bit SPR subregs.
/dports/biology/biosig/biosig-2.3.3/biosig4matlab/t200_FileAccess/
H A Dseof.m32 status = (HDR.FILE.POS >= HDR.SPR*HDR.NRec);
38 status = (HDR.FILE.POS >= HDR.SPR);
H A Dhdr2ascii.m92 if isfield(HDR,'NRec') && isfield(HDR,'SPR')
93 fprintf(fid,'Number_of_Samples\t= %i\n',HDR.NRec*HDR.SPR);
154 if ~isfield(HDR.AS,'SPR'),
155 HDR.AS.SPR = repmat(HDR.SPR,1,HDR.NS);
158 HDR.AS.SampleRate = HDR.AS.SPR/HDR.SPR*HDR.SampleRate;
/dports/net/openmpi/openmpi-4.1.1/opal/mca/patcher/overwrite/
H A Dpatcher_overwrite_module.c173 static unsigned int mtspr(unsigned int SPR, unsigned int RS) { in mtspr() argument
174 return (31<<26) + (RS<<21) + ((SPR&0x1f)<<16) + ((SPR>>5)<<11) + (467<<1); in mtspr()
/dports/net/openmpi3/openmpi-3.1.6/opal/mca/patcher/overwrite/
H A Dpatcher_overwrite_module.c173 static unsigned int mtspr(unsigned int SPR, unsigned int RS) { in mtspr() argument
174 return (31<<26) + (RS<<21) + ((SPR&0x1f)<<16) + ((SPR>>5)<<11) + (467<<1); in mtspr()
/dports/cad/gmsh/gmsh-4.9.2-source/contrib/hxt/tetMesh/src/
H A Dhxt_tetOpti.c267 newLocal[threadID].SPR.dateOfLastCheck = 0; in threadLocals_create()
268 newLocal[threadID].SPR.dateOfLastCreation = 0; in threadLocals_create()
269 newLocal[threadID].SPR.maxSearchNodes = 500; in threadLocals_create()
430 if(locals[threadID].SPR.dateOfLastCheck > lastCheck) in SPRDates_update()
431 lastCheck = locals[threadID].SPR.dateOfLastCheck; in SPRDates_update()
437 locals[threadID].SPR.dateOfLastCheck = lastCheck; in SPRDates_update()
438 locals[threadID].SPR.dateOfLastCreation = lastCheck; in SPRDates_update()
/dports/biology/biosig/biosig-2.3.3/biosig4c++/mex/
H A DmexSLOAD.cpp511 plhs[0] = mxCreateDoubleMatrix(NS, hdr->NRec*hdr->SPR, mxREAL); in mexFunction()
513 plhs[0] = mxCreateDoubleMatrix(hdr->NRec*hdr->SPR, NS, mxREAL); in mexFunction()
558 mxSetField(HDR,0,"SPR",mxCreateDoubleScalar(hdr->SPR)); in mexFunction()
561 mxSetField(HDR,0,"Dur",mxCreateDoubleScalar(hdr->SPR/hdr->SampleRate)); in mexFunction()
596 mxArray *SPR = mxCreateDoubleMatrix(1,NS, mxREAL); in mexFunction() local
613 *(mxGetPr(SPR)+k1) = (double)hdr->CHANNEL[k].SPR; in mexFunction()
665 mxSetField(tmp2,0,"SPR",SPR); in mexFunction()
/dports/biology/hyphy/hyphy-2.5.33/res/TemplateBatchFiles/
H A DdoSPRSwap.bf102 fprintf (stdout, "\n\tRestarting SPR on the better tree.");
131 …fprintf (stdout,"\n\n\t Improved SPR ", Format(taxonCounter,0,0)," taxa tree is ", bestTree, " wit…
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td381 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
382 let AltOrders = [(add (decimate SPR, 2), SPR),
383 (add (decimate SPR, 4),
384 (decimate SPR, 2),
385 (decimate (rotl SPR, 1), 4),
386 (decimate (rotl SPR, 1), 2))];
394 let AltOrders = [(add (decimate HPR, 2), SPR),
405 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
430 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
435 // 32-bit SPR subregs).
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td381 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
382 let AltOrders = [(add (decimate SPR, 2), SPR),
383 (add (decimate SPR, 4),
384 (decimate SPR, 2),
385 (decimate (rotl SPR, 1), 4),
386 (decimate (rotl SPR, 1), 2))];
394 let AltOrders = [(add (decimate HPR, 2), SPR),
405 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
430 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
435 // 32-bit SPR subregs).
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/
H A DARMRegisterInfo.td370 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
371 let AltOrders = [(add (decimate SPR, 2), SPR),
372 (add (decimate SPR, 4),
373 (decimate SPR, 2),
374 (decimate (rotl SPR, 1), 4),
375 (decimate (rotl SPR, 1), 2))];
383 let AltOrders = [(add (decimate HPR, 2), SPR),
394 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
419 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
424 // 32-bit SPR subregs).
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/
H A DARMRegisterInfo.td381 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
382 let AltOrders = [(add (decimate SPR, 2), SPR),
383 (add (decimate SPR, 4),
384 (decimate SPR, 2),
385 (decimate (rotl SPR, 1), 4),
386 (decimate (rotl SPR, 1), 2))];
394 let AltOrders = [(add (decimate HPR, 2), SPR),
405 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
430 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
435 // 32-bit SPR subregs).
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td370 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
371 let AltOrders = [(add (decimate SPR, 2), SPR),
372 (add (decimate SPR, 4),
373 (decimate SPR, 2),
374 (decimate (rotl SPR, 1), 4),
375 (decimate (rotl SPR, 1), 2))];
383 let AltOrders = [(add (decimate HPR, 2), SPR),
394 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
419 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
424 // 32-bit SPR subregs).
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td370 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
371 let AltOrders = [(add (decimate SPR, 2), SPR),
372 (add (decimate SPR, 4),
373 (decimate SPR, 2),
374 (decimate (rotl SPR, 1), 4),
375 (decimate (rotl SPR, 1), 2))];
383 let AltOrders = [(add (decimate HPR, 2), SPR),
394 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
419 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
424 // 32-bit SPR subregs).
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/
H A DARMRegisterInfo.td370 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
371 let AltOrders = [(add (decimate SPR, 2), SPR),
372 (add (decimate SPR, 4),
373 (decimate SPR, 2),
374 (decimate (rotl SPR, 1), 4),
375 (decimate (rotl SPR, 1), 2))];
383 let AltOrders = [(add (decimate HPR, 2), SPR),
394 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
419 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
424 // 32-bit SPR subregs).
[all …]

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