| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 352 unsigned &SrcReg2, int &Mask, int &Value) const override;
355 unsigned SrcReg2, int Mask, int Value,
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 352 unsigned &SrcReg2, int &Mask, int &Value) const override;
355 unsigned SrcReg2, int Mask, int Value,
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 354 unsigned &SrcReg2, int &Mask, int &Value) const override;
357 unsigned SrcReg2, int Mask, int Value,
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1415 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1417 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1418 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1427 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1436 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1763 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1764 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1428 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1430 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1431 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1439 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1440 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1447 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1449 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1776 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1777 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1781 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1415 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1417 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1418 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1427 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1436 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1763 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1764 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1428 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1430 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1431 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1439 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1440 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1447 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1449 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1776 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1777 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1781 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1412 unsigned SrcReg2 = 0;
1414 SrcReg2 = getRegForValue(Src2Value);
1415 if (SrcReg2 == 0) return false;
1423 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1424 if (SrcReg2 == 0) return false;
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1433 .addReg(SrcReg1).addReg(SrcReg2));
1760 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in ExpandCMP_SWAP_64()
1761 if (SrcReg2 == 0) return false;
1765 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1412 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1414 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1415 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1423 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1424 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1433 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1760 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1761 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1765 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1417 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1419 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1420 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1428 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1429 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1436 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1438 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1765 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1766 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1770 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1415 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1417 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1418 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1427 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1436 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1763 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1764 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1412 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1414 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1415 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1423 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1424 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1433 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1760 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1761 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1765 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1428 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1430 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1431 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1439 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1440 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1447 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1449 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1776 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1777 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1781 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1412 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1414 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1415 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1423 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1424 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1433 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1760 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1761 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1765 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1412 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1414 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1415 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1423 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1424 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1433 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1760 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1761 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1765 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1417 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1419 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1420 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1428 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1429 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1436 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1438 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1765 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1766 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1770 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1437 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1439 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1440 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1448 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1449 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1456 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1458 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1786 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1787 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1791 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1438 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1440 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1441 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1449 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1450 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1457 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1459 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1787 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1788 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1792 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1438 unsigned SrcReg2 = 0;
1440 SrcReg2 = getRegForValue(Src2Value);
1441 if (SrcReg2 == 0) return false;
1449 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1450 if (SrcReg2 == 0) return false;
1457 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1459 .addReg(SrcReg1).addReg(SrcReg2));
1787 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1788 if (SrcReg2 == 0) return false;
1792 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1412 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1414 SrcReg2 = getRegForValue(Src2Value); in ARMEmitCmp()
1415 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1423 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1424 if (SrcReg2 == 0) return false; in ARMEmitCmp()
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1433 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1760 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1761 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1765 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 222 Register &SrcReg2, int &CmpMask,
227 Register SrcReg2, int CmpMask, int CmpValue,
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 222 Register &SrcReg2, int &CmpMask,
227 Register SrcReg2, int CmpMask, int CmpValue,
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 222 Register &SrcReg2, int &CmpMask,
227 Register SrcReg2, int CmpMask, int CmpValue,
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 868 unsigned SrcReg2 = 0; in PPCEmitCmp() local
870 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
871 if (SrcReg2 == 0) in PPCEmitCmp()
951 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
953 SrcReg2 = ExtReg; in PPCEmitCmp()
959 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1360 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1361 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1365 std::swap(SrcReg1, SrcReg2); in SelectBinaryIntOp()
1368 .addReg(SrcReg1).addReg(SrcReg2); in SelectBinaryIntOp()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 925 unsigned SrcReg2 = 0; in PPCEmitCmp() local
927 SrcReg2 = getRegForValue(SrcValue2); in PPCEmitCmp()
928 if (SrcReg2 == 0) in PPCEmitCmp()
940 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
942 SrcReg2 = ExtReg; in PPCEmitCmp()
948 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
1349 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
1350 if (SrcReg2 == 0) return false; in SelectBinaryIntOp()
1354 std::swap(SrcReg1, SrcReg2); in SelectBinaryIntOp()
1357 .addReg(SrcReg1).addReg(SrcReg2); in SelectBinaryIntOp()
|