| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/compiler-rt/include/profile/ |
| H A D | InstrProfData.inc | 455 getValueProfRecordNext(ValueProfRecord *VPR);
457 getValueProfRecordValueData(ValueProfRecord *VPR);
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/include/llvm/ProfileData/ |
| H A D | InstrProfData.inc | 455 getValueProfRecordNext(ValueProfRecord *VPR);
457 getValueProfRecordValueData(ValueProfRecord *VPR);
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/compiler-rt/include/profile/ |
| H A D | InstrProfData.inc | 456 getValueProfRecordNext(ValueProfRecord *VPR);
458 getValueProfRecordValueData(ValueProfRecord *VPR);
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/compiler-rt/include/profile/ |
| H A D | InstrProfData.inc | 456 getValueProfRecordNext(ValueProfRecord *VPR);
458 getValueProfRecordValueData(ValueProfRecord *VPR);
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/include/llvm/ProfileData/ |
| H A D | InstrProfData.inc | 456 getValueProfRecordNext(ValueProfRecord *VPR);
458 getValueProfRecordValueData(ValueProfRecord *VPR);
|
| /dports/devel/nextpnr/nextpnr-48cd407/ |
| H A D | README.md | 228 - [VPR/VTR](https://verilogtorouting.org/)
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1314 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1325 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1405 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1499 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
1683 .addReg(ARM::VPR, RegState::Define); in CMSERestoreFPRegsV81()
|
| /dports/x11/terminology/terminology-1.9.0/ |
| H A D | ChangeLog | 129 * Fixes, along with tests, on handling the following escape codes: VPR,
|
| H A D | NEWS | 179 * Fixes, along with tests, on handling the following escape codes: VPR,
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 2388 // System level VPR/P0 -> GPR
2389 let Uses = [VPR] in
2459 // System level GPR -> VPR/P0
2460 let Defs = [VPR] in
2743 let Uses = [VPR] in {
2761 let Defs = [VPR] in {
|
| H A D | ARMLowOverheadLoops.cpp | 516 if (!MO.isReg() || MO.getReg() != ARM::VPR) in ValidateMVEInst()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 2388 // System level VPR/P0 -> GPR
2389 let Uses = [VPR] in
2459 // System level GPR -> VPR/P0
2460 let Defs = [VPR] in
2743 let Uses = [VPR] in {
2761 let Defs = [VPR] in {
|
| H A D | ARMLowOverheadLoops.cpp | 516 if (!MO.isReg() || MO.getReg() != ARM::VPR) in ValidateMVEInst()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 2388 // System level VPR/P0 -> GPR
2389 let Uses = [VPR] in
2459 // System level GPR -> VPR/P0
2460 let Defs = [VPR] in
2743 let Uses = [VPR] in {
2761 let Defs = [VPR] in {
|
| H A D | ARMLowOverheadLoops.cpp | 516 if (!MO.isReg() || MO.getReg() != ARM::VPR) in ValidateMVEInst()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 2354 // System level VPR/P0 -> GPR
2355 let Uses = [VPR] in
2423 // System level GPR -> VPR/P0
2424 let Defs = [VPR] in
2706 let Uses = [VPR] in {
2724 let Defs = [VPR] in {
|
| /dports/devel/avr-gcc/gcc-10.2.0/gcc/config/arm/ |
| H A D | unspecs.md | 250 VUNSPEC_VSCCLRM_VPR ; Represent the clearing of VPR with vscclrm
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1200 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1211 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1289 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1383 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1189 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1200 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1278 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1372 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1200 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1211 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1289 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1383 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1189 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1200 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1278 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1372 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1200 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1211 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1289 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1383 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 5920 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
5941 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6131 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6598 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6635 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6645 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6646 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 5918 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
5939 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6129 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6596 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6633 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6643 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6644 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 5898 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
5919 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeForVMRSandVMSR()
6092 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeVSCCLRM()
6569 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVCMP()
6606 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMveVCTP()
6616 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
6617 Inst.addOperand(MCOperand::createReg(ARM::VPR)); in DecodeMVEVPNOT()
|