1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "ARMBaseInstrInfo.h"
10 #include "MCTargetDesc/ARMAddressingModes.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMMCTargetDesc.h"
13 #include "TargetInfo/ARMTargetInfo.h"
14 #include "Utils/ARMBaseInfo.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
17 #include "llvm/MC/MCFixedLenDisassembler.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/SubtargetFeature.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include <algorithm>
28 #include <cassert>
29 #include <cstdint>
30 #include <vector>
31
32 using namespace llvm;
33
34 #define DEBUG_TYPE "arm-disassembler"
35
36 using DecodeStatus = MCDisassembler::DecodeStatus;
37
38 namespace {
39
40 // Handles the condition code status of instructions in IT blocks
41 class ITStatus
42 {
43 public:
44 // Returns the condition code for instruction in IT block
getITCC()45 unsigned getITCC() {
46 unsigned CC = ARMCC::AL;
47 if (instrInITBlock())
48 CC = ITStates.back();
49 return CC;
50 }
51
52 // Advances the IT block state to the next T or E
advanceITState()53 void advanceITState() {
54 ITStates.pop_back();
55 }
56
57 // Returns true if the current instruction is in an IT block
instrInITBlock()58 bool instrInITBlock() {
59 return !ITStates.empty();
60 }
61
62 // Returns true if current instruction is the last instruction in an IT block
instrLastInITBlock()63 bool instrLastInITBlock() {
64 return ITStates.size() == 1;
65 }
66
67 // Called when decoding an IT instruction. Sets the IT state for
68 // the following instructions that for the IT block. Firstcond
69 // corresponds to the field in the IT instruction encoding; Mask
70 // is in the MCOperand format in which 1 means 'else' and 0 'then'.
setITState(char Firstcond,char Mask)71 void setITState(char Firstcond, char Mask) {
72 // (3 - the number of trailing zeros) is the number of then / else.
73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
75 assert(NumTZ <= 3 && "Invalid IT mask!");
76 // push condition codes onto the stack the correct order for the pops
77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78 unsigned Else = (Mask >> Pos) & 1;
79 ITStates.push_back(CCBits ^ Else);
80 }
81 ITStates.push_back(CCBits);
82 }
83
84 private:
85 std::vector<unsigned char> ITStates;
86 };
87
88 class VPTStatus
89 {
90 public:
getVPTPred()91 unsigned getVPTPred() {
92 unsigned Pred = ARMVCC::None;
93 if (instrInVPTBlock())
94 Pred = VPTStates.back();
95 return Pred;
96 }
97
advanceVPTState()98 void advanceVPTState() {
99 VPTStates.pop_back();
100 }
101
instrInVPTBlock()102 bool instrInVPTBlock() {
103 return !VPTStates.empty();
104 }
105
instrLastInVPTBlock()106 bool instrLastInVPTBlock() {
107 return VPTStates.size() == 1;
108 }
109
setVPTState(char Mask)110 void setVPTState(char Mask) {
111 // (3 - the number of trailing zeros) is the number of then / else.
112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
113 assert(NumTZ <= 3 && "Invalid VPT mask!");
114 // push predicates onto the stack the correct order for the pops
115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116 bool T = ((Mask >> Pos) & 1) == 0;
117 if (T)
118 VPTStates.push_back(ARMVCC::Then);
119 else
120 VPTStates.push_back(ARMVCC::Else);
121 }
122 VPTStates.push_back(ARMVCC::Then);
123 }
124
125 private:
126 SmallVector<unsigned char, 4> VPTStates;
127 };
128
129 /// ARM disassembler for all ARM platforms.
130 class ARMDisassembler : public MCDisassembler {
131 public:
ARMDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
133 MCDisassembler(STI, Ctx) {
134 }
135
136 ~ARMDisassembler() override = default;
137
138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
139 ArrayRef<uint8_t> Bytes, uint64_t Address,
140 raw_ostream &CStream) const override;
141
142 private:
143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
144 ArrayRef<uint8_t> Bytes, uint64_t Address,
145 raw_ostream &CStream) const;
146
147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
148 ArrayRef<uint8_t> Bytes, uint64_t Address,
149 raw_ostream &CStream) const;
150
151 mutable ITStatus ITBlock;
152 mutable VPTStatus VPTBlock;
153
154 DecodeStatus AddThumbPredicate(MCInst&) const;
155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
156 };
157
158 } // end anonymous namespace
159
Check(DecodeStatus & Out,DecodeStatus In)160 static bool Check(DecodeStatus &Out, DecodeStatus In) {
161 switch (In) {
162 case MCDisassembler::Success:
163 // Out stays the same.
164 return true;
165 case MCDisassembler::SoftFail:
166 Out = In;
167 return true;
168 case MCDisassembler::Fail:
169 Out = In;
170 return false;
171 }
172 llvm_unreachable("Invalid DecodeStatus!");
173 }
174
175 // Forward declare these because the autogenerated code will reference them.
176 // Definitions are further down.
177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
178 uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
184 uint64_t Address, const void *Decoder);
185 static DecodeStatus
186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
189 unsigned RegNo, uint64_t Address,
190 const void *Decoder);
191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
192 unsigned RegNo, uint64_t Address,
193 const void *Decoder);
194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
195 unsigned RegNo, uint64_t Address,
196 const void *Decoder);
197 static DecodeStatus DecodeGPRwithZRnospRegisterClass(
198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
210 uint64_t Address,
211 const void *Decoder);
212 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
213 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
215 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
217 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
223 unsigned RegNo,
224 uint64_t Address,
225 const void *Decoder);
226 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
237 unsigned RegNo, uint64_t Address,
238 const void *Decoder);
239
240 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250
251 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
256 unsigned Insn,
257 uint64_t Address,
258 const void *Decoder);
259 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
266 uint64_t Address, const void *Decoder);
267
268 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
269 unsigned Insn,
270 uint64_t Adddress,
271 const void *Decoder);
272 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
343 uint64_t Address, const void *Decoder);
344 template<int shift>
345 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
346 uint64_t Address, const void *Decoder);
347 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
348 uint64_t Address, const void *Decoder);
349 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
350 uint64_t Address, const void *Decoder);
351 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
352 uint64_t Address, const void *Decoder);
353 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
354 uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
356 uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
358 uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
360 uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
362 uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
364 uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
366 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
368 uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
370 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
372 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
374 uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
376 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
378 uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
380 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
382 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
384 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
386 uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
388 uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
390 uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
392 uint64_t Address, const void *Decoder);
393 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
394 uint64_t Address, const void *Decoder);
395 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
396 uint64_t Address, const void *Decoder);
397 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
398 unsigned Val,
399 uint64_t Address,
400 const void *Decoder);
401
402 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
403 uint64_t Address, const void *Decoder);
404 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
405 uint64_t Address, const void *Decoder);
406 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
407 uint64_t Address, const void *Decoder);
408 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
409 uint64_t Address, const void *Decoder);
410 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
411 uint64_t Address, const void *Decoder);
412 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
413 uint64_t Address, const void *Decoder);
414 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
415 uint64_t Address, const void *Decoder);
416 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
417 uint64_t Address, const void *Decoder);
418 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
419 uint64_t Address, const void *Decoder);
420 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
421 uint64_t Address, const void *Decoder);
422 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
423 uint64_t Address, const void* Decoder);
424 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
425 uint64_t Address, const void* Decoder);
426 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
427 uint64_t Address, const void* Decoder);
428 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
429 uint64_t Address, const void* Decoder);
430 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
431 uint64_t Address, const void *Decoder);
432 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val,
433 uint64_t Address, const void *Decoder);
434 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
435 uint64_t Address, const void *Decoder);
436 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
437 uint64_t Address,
438 const void *Decoder);
439 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
440 uint64_t Address, const void *Decoder);
441 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
442 uint64_t Address, const void *Decoder);
443 template<int shift>
444 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
445 uint64_t Address, const void *Decoder);
446 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
447 uint64_t Address, const void *Decoder);
448 template<int shift>
449 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
450 uint64_t Address, const void *Decoder);
451 template<int shift, int WriteBack>
452 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
453 uint64_t Address, const void *Decoder);
454 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
455 uint64_t Address, const void *Decoder);
456 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
457 uint64_t Address, const void *Decoder);
458 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
459 uint64_t Address, const void *Decoder);
460 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
461 uint64_t Address, const void *Decoder);
462 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
463 uint64_t Address, const void *Decoder);
464 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
465 uint64_t Address, const void *Decoder);
466 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
467 uint64_t Address, const void *Decoder);
468 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
469 uint64_t Address, const void *Decoder);
470 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
471 uint64_t Address, const void *Decoder);
472 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
473 uint64_t Address, const void *Decoder);
474 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
475 uint64_t Address, const void *Decoder);
476 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
477 uint64_t Address, const void *Decoder);
478 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
479 uint64_t Address, const void *Decoder);
480 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
481 uint64_t Address, const void *Decoder);
482 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
483 uint64_t Address, const void *Decoder);
484 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
485 uint64_t Address, const void *Decoder);
486 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
487 uint64_t Address, const void *Decoder);
488
489 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
490 uint64_t Address, const void *Decoder);
491 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
492 uint64_t Address, const void *Decoder);
493 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
494 uint64_t Address, const void *Decoder);
495
496 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
497 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
498 uint64_t Address, const void *Decoder);
499 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
500 uint64_t Address,
501 const void *Decoder);
502 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
503 uint64_t Address,
504 const void *Decoder);
505 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
506 const void *Decoder);
507 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
508 uint64_t Address,
509 const void *Decoder);
510 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
511 const void *Decoder);
512 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
513 uint64_t Address, const void *Decoder);
514 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
515 uint64_t Address, const void *Decoder);
516 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val,
517 uint64_t Address,
518 const void *Decoder);
519 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val,
520 uint64_t Address,
521 const void *Decoder);
522 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val,
523 uint64_t Address,
524 const void *Decoder);
525 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst,
526 unsigned Val,
527 uint64_t Address,
528 const void *Decoder);
529 template<bool Writeback>
530 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
531 uint64_t Address,
532 const void *Decoder);
533 template<int shift>
534 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
535 uint64_t Address, const void *Decoder);
536 template<int shift>
537 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
538 uint64_t Address, const void *Decoder);
539 template<int shift>
540 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
541 uint64_t Address, const void *Decoder);
542 template<unsigned MinLog, unsigned MaxLog>
543 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
544 uint64_t Address,
545 const void *Decoder);
546 template<unsigned start>
547 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
548 uint64_t Address,
549 const void *Decoder);
550 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
551 uint64_t Address,
552 const void *Decoder);
553 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
554 uint64_t Address,
555 const void *Decoder);
556 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
557 uint64_t Address, const void *Decoder);
558 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
559 uint64_t Address, const void *Decoder);
560 template<bool scalar, OperandDecoder predicate_decoder>
561 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
562 uint64_t Address, const void *Decoder);
563 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
564 uint64_t Address, const void *Decoder);
565 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
566 uint64_t Address, const void *Decoder);
567 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
568 uint64_t Address,
569 const void *Decoder);
570 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
571 uint64_t Address, const void *Decoder);
572
573 #include "ARMGenDisassemblerTables.inc"
574
createARMDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)575 static MCDisassembler *createARMDisassembler(const Target &T,
576 const MCSubtargetInfo &STI,
577 MCContext &Ctx) {
578 return new ARMDisassembler(STI, Ctx);
579 }
580
581 // Post-decoding checks
checkDecodedInstruction(MCInst & MI,uint64_t & Size,uint64_t Address,raw_ostream & CS,uint32_t Insn,DecodeStatus Result)582 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
583 uint64_t Address, raw_ostream &CS,
584 uint32_t Insn,
585 DecodeStatus Result) {
586 switch (MI.getOpcode()) {
587 case ARM::HVC: {
588 // HVC is undefined if condition = 0xf otherwise upredictable
589 // if condition != 0xe
590 uint32_t Cond = (Insn >> 28) & 0xF;
591 if (Cond == 0xF)
592 return MCDisassembler::Fail;
593 if (Cond != 0xE)
594 return MCDisassembler::SoftFail;
595 return Result;
596 }
597 case ARM::t2ADDri:
598 case ARM::t2ADDri12:
599 case ARM::t2ADDrr:
600 case ARM::t2ADDrs:
601 case ARM::t2SUBri:
602 case ARM::t2SUBri12:
603 case ARM::t2SUBrr:
604 case ARM::t2SUBrs:
605 if (MI.getOperand(0).getReg() == ARM::SP &&
606 MI.getOperand(1).getReg() != ARM::SP)
607 return MCDisassembler::SoftFail;
608 return Result;
609 default: return Result;
610 }
611 }
612
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const613 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
614 ArrayRef<uint8_t> Bytes,
615 uint64_t Address,
616 raw_ostream &CS) const {
617 if (STI.getFeatureBits()[ARM::ModeThumb])
618 return getThumbInstruction(MI, Size, Bytes, Address, CS);
619 return getARMInstruction(MI, Size, Bytes, Address, CS);
620 }
621
getARMInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const622 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
623 ArrayRef<uint8_t> Bytes,
624 uint64_t Address,
625 raw_ostream &CS) const {
626 CommentStream = &CS;
627
628 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
629 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
630 "mode!");
631
632 // We want to read exactly 4 bytes of data.
633 if (Bytes.size() < 4) {
634 Size = 0;
635 return MCDisassembler::Fail;
636 }
637
638 // Encoded as a small-endian 32-bit word in the stream.
639 uint32_t Insn =
640 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
641
642 // Calling the auto-generated decoder function.
643 DecodeStatus Result =
644 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
645 if (Result != MCDisassembler::Fail) {
646 Size = 4;
647 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
648 }
649
650 struct DecodeTable {
651 const uint8_t *P;
652 bool DecodePred;
653 };
654
655 const DecodeTable Tables[] = {
656 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false},
657 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true},
658 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false},
659 {DecoderTablev8Crypto32, false},
660 };
661
662 for (auto Table : Tables) {
663 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
664 if (Result != MCDisassembler::Fail) {
665 Size = 4;
666 // Add a fake predicate operand, because we share these instruction
667 // definitions with Thumb2 where these instructions are predicable.
668 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
669 return MCDisassembler::Fail;
670 return Result;
671 }
672 }
673
674 Result =
675 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
676 if (Result != MCDisassembler::Fail) {
677 Size = 4;
678 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
679 }
680
681 Size = 4;
682 return MCDisassembler::Fail;
683 }
684
685 namespace llvm {
686
687 extern const MCInstrDesc ARMInsts[];
688
689 } // end namespace llvm
690
691 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
692 /// immediate Value in the MCInst. The immediate Value has had any PC
693 /// adjustment made by the caller. If the instruction is a branch instruction
694 /// then isBranch is true, else false. If the getOpInfo() function was set as
695 /// part of the setupForSymbolicDisassembly() call then that function is called
696 /// to get any symbolic information at the Address for this instruction. If
697 /// that returns non-zero then the symbolic information it returns is used to
698 /// create an MCExpr and that is added as an operand to the MCInst. If
699 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
700 /// Value is done and if a symbol is found an MCExpr is created with that, else
701 /// an MCExpr with Value is created. This function returns true if it adds an
702 /// operand to the MCInst and false otherwise.
tryAddingSymbolicOperand(uint64_t Address,int32_t Value,bool isBranch,uint64_t InstSize,MCInst & MI,const void * Decoder)703 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
704 bool isBranch, uint64_t InstSize,
705 MCInst &MI, const void *Decoder) {
706 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
707 // FIXME: Does it make sense for value to be negative?
708 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
709 /* Offset */ 0, InstSize);
710 }
711
712 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
713 /// referenced by a load instruction with the base register that is the Pc.
714 /// These can often be values in a literal pool near the Address of the
715 /// instruction. The Address of the instruction and its immediate Value are
716 /// used as a possible literal pool entry. The SymbolLookUp call back will
717 /// return the name of a symbol referenced by the literal pool's entry if
718 /// the referenced address is that of a symbol. Or it will return a pointer to
719 /// a literal 'C' string if the referenced address of the literal pool's entry
720 /// is an address into a section with 'C' string literals.
tryAddingPcLoadReferenceComment(uint64_t Address,int Value,const void * Decoder)721 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
722 const void *Decoder) {
723 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
724 Dis->tryAddingPcLoadReferenceComment(Value, Address);
725 }
726
727 // Thumb1 instructions don't have explicit S bits. Rather, they
728 // implicitly set CPSR. Since it's not represented in the encoding, the
729 // auto-generated decoder won't inject the CPSR operand. We need to fix
730 // that as a post-pass.
AddThumb1SBit(MCInst & MI,bool InITBlock)731 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
732 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
733 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
734 MCInst::iterator I = MI.begin();
735 for (unsigned i = 0; i < NumOps; ++i, ++I) {
736 if (I == MI.end()) break;
737 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
738 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
739 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
740 return;
741 }
742 }
743
744 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
745 }
746
isVectorPredicable(unsigned Opcode)747 static bool isVectorPredicable(unsigned Opcode) {
748 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
749 unsigned short NumOps = ARMInsts[Opcode].NumOperands;
750 for (unsigned i = 0; i < NumOps; ++i) {
751 if (ARM::isVpred(OpInfo[i].OperandType))
752 return true;
753 }
754 return false;
755 }
756
757 // Most Thumb instructions don't have explicit predicates in the
758 // encoding, but rather get their predicates from IT context. We need
759 // to fix up the predicate operands using this context information as a
760 // post-pass.
761 MCDisassembler::DecodeStatus
AddThumbPredicate(MCInst & MI) const762 ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
763 MCDisassembler::DecodeStatus S = Success;
764
765 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
766
767 // A few instructions actually have predicates encoded in them. Don't
768 // try to overwrite it if we're seeing one of those.
769 switch (MI.getOpcode()) {
770 case ARM::tBcc:
771 case ARM::t2Bcc:
772 case ARM::tCBZ:
773 case ARM::tCBNZ:
774 case ARM::tCPS:
775 case ARM::t2CPS3p:
776 case ARM::t2CPS2p:
777 case ARM::t2CPS1p:
778 case ARM::t2CSEL:
779 case ARM::t2CSINC:
780 case ARM::t2CSINV:
781 case ARM::t2CSNEG:
782 case ARM::tMOVSr:
783 case ARM::tSETEND:
784 // Some instructions (mostly conditional branches) are not
785 // allowed in IT blocks.
786 if (ITBlock.instrInITBlock())
787 S = SoftFail;
788 else
789 return Success;
790 break;
791 case ARM::t2HINT:
792 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
793 S = SoftFail;
794 break;
795 case ARM::tB:
796 case ARM::t2B:
797 case ARM::t2TBB:
798 case ARM::t2TBH:
799 // Some instructions (mostly unconditional branches) can
800 // only appears at the end of, or outside of, an IT.
801 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
802 S = SoftFail;
803 break;
804 default:
805 break;
806 }
807
808 // Warn on non-VPT predicable instruction in a VPT block and a VPT
809 // predicable instruction in an IT block
810 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
811 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
812 S = SoftFail;
813
814 // If we're in an IT/VPT block, base the predicate on that. Otherwise,
815 // assume a predicate of AL.
816 unsigned CC = ARMCC::AL;
817 unsigned VCC = ARMVCC::None;
818 if (ITBlock.instrInITBlock()) {
819 CC = ITBlock.getITCC();
820 ITBlock.advanceITState();
821 } else if (VPTBlock.instrInVPTBlock()) {
822 VCC = VPTBlock.getVPTPred();
823 VPTBlock.advanceVPTState();
824 }
825
826 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
827 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
828
829 MCInst::iterator CCI = MI.begin();
830 for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
831 if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
832 }
833
834 if (ARMInsts[MI.getOpcode()].isPredicable()) {
835 CCI = MI.insert(CCI, MCOperand::createImm(CC));
836 ++CCI;
837 if (CC == ARMCC::AL)
838 MI.insert(CCI, MCOperand::createReg(0));
839 else
840 MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
841 } else if (CC != ARMCC::AL) {
842 Check(S, SoftFail);
843 }
844
845 MCInst::iterator VCCI = MI.begin();
846 unsigned VCCPos;
847 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
848 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
849 }
850
851 if (isVectorPredicable(MI.getOpcode())) {
852 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
853 ++VCCI;
854 if (VCC == ARMVCC::None)
855 MI.insert(VCCI, MCOperand::createReg(0));
856 else
857 MI.insert(VCCI, MCOperand::createReg(ARM::P0));
858 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
859 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
860 VCCPos + 2, MCOI::TIED_TO);
861 assert(TiedOp >= 0 &&
862 "Inactive register in vpred_r is not tied to an output!");
863 MI.insert(VCCI, MI.getOperand(TiedOp));
864 }
865 } else if (VCC != ARMVCC::None) {
866 Check(S, SoftFail);
867 }
868
869 return S;
870 }
871
872 // Thumb VFP instructions are a special case. Because we share their
873 // encodings between ARM and Thumb modes, and they are predicable in ARM
874 // mode, the auto-generated decoder will give them an (incorrect)
875 // predicate operand. We need to rewrite these operands based on the IT
876 // context as a post-pass.
UpdateThumbVFPPredicate(DecodeStatus & S,MCInst & MI) const877 void ARMDisassembler::UpdateThumbVFPPredicate(
878 DecodeStatus &S, MCInst &MI) const {
879 unsigned CC;
880 CC = ITBlock.getITCC();
881 if (CC == 0xF)
882 CC = ARMCC::AL;
883 if (ITBlock.instrInITBlock())
884 ITBlock.advanceITState();
885 else if (VPTBlock.instrInVPTBlock()) {
886 CC = VPTBlock.getVPTPred();
887 VPTBlock.advanceVPTState();
888 }
889
890 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
891 MCInst::iterator I = MI.begin();
892 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
893 for (unsigned i = 0; i < NumOps; ++i, ++I) {
894 if (OpInfo[i].isPredicate() ) {
895 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
896 Check(S, SoftFail);
897 I->setImm(CC);
898 ++I;
899 if (CC == ARMCC::AL)
900 I->setReg(0);
901 else
902 I->setReg(ARM::CPSR);
903 return;
904 }
905 }
906 }
907
getThumbInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const908 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
909 ArrayRef<uint8_t> Bytes,
910 uint64_t Address,
911 raw_ostream &CS) const {
912 CommentStream = &CS;
913
914 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
915 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
916
917 // We want to read exactly 2 bytes of data.
918 if (Bytes.size() < 2) {
919 Size = 0;
920 return MCDisassembler::Fail;
921 }
922
923 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
924 DecodeStatus Result =
925 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
926 if (Result != MCDisassembler::Fail) {
927 Size = 2;
928 Check(Result, AddThumbPredicate(MI));
929 return Result;
930 }
931
932 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
933 STI);
934 if (Result) {
935 Size = 2;
936 bool InITBlock = ITBlock.instrInITBlock();
937 Check(Result, AddThumbPredicate(MI));
938 AddThumb1SBit(MI, InITBlock);
939 return Result;
940 }
941
942 Result =
943 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
944 if (Result != MCDisassembler::Fail) {
945 Size = 2;
946
947 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
948 // the Thumb predicate.
949 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
950 Result = MCDisassembler::SoftFail;
951
952 Check(Result, AddThumbPredicate(MI));
953
954 // If we find an IT instruction, we need to parse its condition
955 // code and mask operands so that we can apply them correctly
956 // to the subsequent instructions.
957 if (MI.getOpcode() == ARM::t2IT) {
958 unsigned Firstcond = MI.getOperand(0).getImm();
959 unsigned Mask = MI.getOperand(1).getImm();
960 ITBlock.setITState(Firstcond, Mask);
961
962 // An IT instruction that would give a 'NV' predicate is unpredictable.
963 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
964 CS << "unpredictable IT predicate sequence";
965 }
966
967 return Result;
968 }
969
970 // We want to read exactly 4 bytes of data.
971 if (Bytes.size() < 4) {
972 Size = 0;
973 return MCDisassembler::Fail;
974 }
975
976 uint32_t Insn32 =
977 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
978
979 Result =
980 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
981 if (Result != MCDisassembler::Fail) {
982 Size = 4;
983
984 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
985 // the VPT predicate.
986 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
987 Result = MCDisassembler::SoftFail;
988
989 Check(Result, AddThumbPredicate(MI));
990
991 if (isVPTOpcode(MI.getOpcode())) {
992 unsigned Mask = MI.getOperand(0).getImm();
993 VPTBlock.setVPTState(Mask);
994 }
995
996 return Result;
997 }
998
999 Result =
1000 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
1001 if (Result != MCDisassembler::Fail) {
1002 Size = 4;
1003 bool InITBlock = ITBlock.instrInITBlock();
1004 Check(Result, AddThumbPredicate(MI));
1005 AddThumb1SBit(MI, InITBlock);
1006 return Result;
1007 }
1008
1009 Result =
1010 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
1011 if (Result != MCDisassembler::Fail) {
1012 Size = 4;
1013 Check(Result, AddThumbPredicate(MI));
1014 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
1015 }
1016
1017 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1018 Result =
1019 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
1020 if (Result != MCDisassembler::Fail) {
1021 Size = 4;
1022 UpdateThumbVFPPredicate(Result, MI);
1023 return Result;
1024 }
1025 }
1026
1027 Result =
1028 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
1029 if (Result != MCDisassembler::Fail) {
1030 Size = 4;
1031 return Result;
1032 }
1033
1034 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1035 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
1036 STI);
1037 if (Result != MCDisassembler::Fail) {
1038 Size = 4;
1039 Check(Result, AddThumbPredicate(MI));
1040 return Result;
1041 }
1042 }
1043
1044 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1045 uint32_t NEONLdStInsn = Insn32;
1046 NEONLdStInsn &= 0xF0FFFFFF;
1047 NEONLdStInsn |= 0x04000000;
1048 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
1049 Address, this, STI);
1050 if (Result != MCDisassembler::Fail) {
1051 Size = 4;
1052 Check(Result, AddThumbPredicate(MI));
1053 return Result;
1054 }
1055 }
1056
1057 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1058 uint32_t NEONDataInsn = Insn32;
1059 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1060 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1061 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1062 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
1063 Address, this, STI);
1064 if (Result != MCDisassembler::Fail) {
1065 Size = 4;
1066 Check(Result, AddThumbPredicate(MI));
1067 return Result;
1068 }
1069
1070 uint32_t NEONCryptoInsn = Insn32;
1071 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1072 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1073 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1074 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
1075 Address, this, STI);
1076 if (Result != MCDisassembler::Fail) {
1077 Size = 4;
1078 return Result;
1079 }
1080
1081 uint32_t NEONv8Insn = Insn32;
1082 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1083 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
1084 this, STI);
1085 if (Result != MCDisassembler::Fail) {
1086 Size = 4;
1087 return Result;
1088 }
1089 }
1090
1091 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1092 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
1093 ? DecoderTableThumb2CDE32
1094 : DecoderTableThumb2CoProc32;
1095 Result =
1096 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
1097 if (Result != MCDisassembler::Fail) {
1098 Size = 4;
1099 Check(Result, AddThumbPredicate(MI));
1100 return Result;
1101 }
1102
1103 Size = 0;
1104 return MCDisassembler::Fail;
1105 }
1106
LLVMInitializeARMDisassembler()1107 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() {
1108 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
1109 createARMDisassembler);
1110 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
1111 createARMDisassembler);
1112 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
1113 createARMDisassembler);
1114 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
1115 createARMDisassembler);
1116 }
1117
1118 static const uint16_t GPRDecoderTable[] = {
1119 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1120 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1121 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1122 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1123 };
1124
1125 static const uint16_t CLRMGPRDecoderTable[] = {
1126 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1127 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1128 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1129 ARM::R12, 0, ARM::LR, ARM::APSR
1130 };
1131
DecodeGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1132 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1133 uint64_t Address, const void *Decoder) {
1134 if (RegNo > 15)
1135 return MCDisassembler::Fail;
1136
1137 unsigned Register = GPRDecoderTable[RegNo];
1138 Inst.addOperand(MCOperand::createReg(Register));
1139 return MCDisassembler::Success;
1140 }
1141
DecodeCLRMGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1142 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1143 uint64_t Address,
1144 const void *Decoder) {
1145 if (RegNo > 15)
1146 return MCDisassembler::Fail;
1147
1148 unsigned Register = CLRMGPRDecoderTable[RegNo];
1149 if (Register == 0)
1150 return MCDisassembler::Fail;
1151
1152 Inst.addOperand(MCOperand::createReg(Register));
1153 return MCDisassembler::Success;
1154 }
1155
1156 static DecodeStatus
DecodeGPRnopcRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1157 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1158 uint64_t Address, const void *Decoder) {
1159 DecodeStatus S = MCDisassembler::Success;
1160
1161 if (RegNo == 15)
1162 S = MCDisassembler::SoftFail;
1163
1164 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1165
1166 return S;
1167 }
1168
1169 static DecodeStatus
DecodeGPRwithAPSRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1170 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
1171 uint64_t Address, const void *Decoder) {
1172 DecodeStatus S = MCDisassembler::Success;
1173
1174 if (RegNo == 15)
1175 {
1176 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1177 return MCDisassembler::Success;
1178 }
1179
1180 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1181 return S;
1182 }
1183
1184 static DecodeStatus
DecodeGPRwithZRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1185 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
1186 uint64_t Address, const void *Decoder) {
1187 DecodeStatus S = MCDisassembler::Success;
1188
1189 if (RegNo == 15)
1190 {
1191 Inst.addOperand(MCOperand::createReg(ARM::ZR));
1192 return MCDisassembler::Success;
1193 }
1194
1195 if (RegNo == 13)
1196 Check(S, MCDisassembler::SoftFail);
1197
1198 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1199 return S;
1200 }
1201
1202 static DecodeStatus
DecodeGPRwithZRnospRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1203 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1204 uint64_t Address, const void *Decoder) {
1205 DecodeStatus S = MCDisassembler::Success;
1206 if (RegNo == 13)
1207 return MCDisassembler::Fail;
1208 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1209 return S;
1210 }
1211
DecodetGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1212 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1213 uint64_t Address, const void *Decoder) {
1214 if (RegNo > 7)
1215 return MCDisassembler::Fail;
1216 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1217 }
1218
1219 static const uint16_t GPRPairDecoderTable[] = {
1220 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
1221 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1222 };
1223
DecodeGPRPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1224 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1225 uint64_t Address, const void *Decoder) {
1226 DecodeStatus S = MCDisassembler::Success;
1227
1228 // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1229 // rather than SoftFail as there is no GPRPair table entry for index 7.
1230 if (RegNo > 13)
1231 return MCDisassembler::Fail;
1232
1233 if (RegNo & 1)
1234 S = MCDisassembler::SoftFail;
1235
1236 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1237 Inst.addOperand(MCOperand::createReg(RegisterPair));
1238 return S;
1239 }
1240
DecodeGPRPairnospRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1241 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
1242 uint64_t Address, const void *Decoder) {
1243 if (RegNo > 13)
1244 return MCDisassembler::Fail;
1245
1246 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1247 Inst.addOperand(MCOperand::createReg(RegisterPair));
1248
1249 if ((RegNo & 1) || RegNo > 10)
1250 return MCDisassembler::SoftFail;
1251 return MCDisassembler::Success;
1252 }
1253
DecodeGPRspRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1254 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1255 uint64_t Address,
1256 const void *Decoder) {
1257 if (RegNo != 13)
1258 return MCDisassembler::Fail;
1259
1260 unsigned Register = GPRDecoderTable[RegNo];
1261 Inst.addOperand(MCOperand::createReg(Register));
1262 return MCDisassembler::Success;
1263 }
1264
DecodetcGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1265 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1266 uint64_t Address, const void *Decoder) {
1267 unsigned Register = 0;
1268 switch (RegNo) {
1269 case 0:
1270 Register = ARM::R0;
1271 break;
1272 case 1:
1273 Register = ARM::R1;
1274 break;
1275 case 2:
1276 Register = ARM::R2;
1277 break;
1278 case 3:
1279 Register = ARM::R3;
1280 break;
1281 case 9:
1282 Register = ARM::R9;
1283 break;
1284 case 12:
1285 Register = ARM::R12;
1286 break;
1287 default:
1288 return MCDisassembler::Fail;
1289 }
1290
1291 Inst.addOperand(MCOperand::createReg(Register));
1292 return MCDisassembler::Success;
1293 }
1294
DecoderGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1295 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1296 uint64_t Address, const void *Decoder) {
1297 DecodeStatus S = MCDisassembler::Success;
1298
1299 const FeatureBitset &featureBits =
1300 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1301
1302 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1303 S = MCDisassembler::SoftFail;
1304
1305 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1306 return S;
1307 }
1308
1309 static const uint16_t SPRDecoderTable[] = {
1310 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1311 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1312 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1313 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1314 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1315 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1316 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1317 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1318 };
1319
DecodeSPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1320 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1321 uint64_t Address, const void *Decoder) {
1322 if (RegNo > 31)
1323 return MCDisassembler::Fail;
1324
1325 unsigned Register = SPRDecoderTable[RegNo];
1326 Inst.addOperand(MCOperand::createReg(Register));
1327 return MCDisassembler::Success;
1328 }
1329
DecodeHPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1330 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1331 uint64_t Address, const void *Decoder) {
1332 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1333 }
1334
1335 static const uint16_t DPRDecoderTable[] = {
1336 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1337 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1338 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1339 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1340 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1341 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1342 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1343 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1344 };
1345
DecodeDPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1346 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1347 uint64_t Address, const void *Decoder) {
1348 const FeatureBitset &featureBits =
1349 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1350
1351 bool hasD32 = featureBits[ARM::FeatureD32];
1352
1353 if (RegNo > 31 || (!hasD32 && RegNo > 15))
1354 return MCDisassembler::Fail;
1355
1356 unsigned Register = DPRDecoderTable[RegNo];
1357 Inst.addOperand(MCOperand::createReg(Register));
1358 return MCDisassembler::Success;
1359 }
1360
DecodeDPR_8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1361 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1362 uint64_t Address, const void *Decoder) {
1363 if (RegNo > 7)
1364 return MCDisassembler::Fail;
1365 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1366 }
1367
DecodeSPR_8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1368 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1369 uint64_t Address, const void *Decoder) {
1370 if (RegNo > 15)
1371 return MCDisassembler::Fail;
1372 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1373 }
1374
1375 static DecodeStatus
DecodeDPR_VFP2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1376 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1377 uint64_t Address, const void *Decoder) {
1378 if (RegNo > 15)
1379 return MCDisassembler::Fail;
1380 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1381 }
1382
1383 static const uint16_t QPRDecoderTable[] = {
1384 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1385 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1386 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1387 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1388 };
1389
DecodeQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1390 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1391 uint64_t Address, const void *Decoder) {
1392 if (RegNo > 31 || (RegNo & 1) != 0)
1393 return MCDisassembler::Fail;
1394 RegNo >>= 1;
1395
1396 unsigned Register = QPRDecoderTable[RegNo];
1397 Inst.addOperand(MCOperand::createReg(Register));
1398 return MCDisassembler::Success;
1399 }
1400
1401 static const uint16_t DPairDecoderTable[] = {
1402 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1403 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1404 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1405 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1406 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1407 ARM::Q15
1408 };
1409
DecodeDPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1410 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1411 uint64_t Address, const void *Decoder) {
1412 if (RegNo > 30)
1413 return MCDisassembler::Fail;
1414
1415 unsigned Register = DPairDecoderTable[RegNo];
1416 Inst.addOperand(MCOperand::createReg(Register));
1417 return MCDisassembler::Success;
1418 }
1419
1420 static const uint16_t DPairSpacedDecoderTable[] = {
1421 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1422 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1423 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1424 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1425 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1426 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1427 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1428 ARM::D28_D30, ARM::D29_D31
1429 };
1430
DecodeDPairSpacedRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1431 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1432 unsigned RegNo,
1433 uint64_t Address,
1434 const void *Decoder) {
1435 if (RegNo > 29)
1436 return MCDisassembler::Fail;
1437
1438 unsigned Register = DPairSpacedDecoderTable[RegNo];
1439 Inst.addOperand(MCOperand::createReg(Register));
1440 return MCDisassembler::Success;
1441 }
1442
DecodePredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1443 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1444 uint64_t Address, const void *Decoder) {
1445 DecodeStatus S = MCDisassembler::Success;
1446 if (Val == 0xF) return MCDisassembler::Fail;
1447 // AL predicate is not allowed on Thumb1 branches.
1448 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1449 return MCDisassembler::Fail;
1450 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1451 Check(S, MCDisassembler::SoftFail);
1452 Inst.addOperand(MCOperand::createImm(Val));
1453 if (Val == ARMCC::AL) {
1454 Inst.addOperand(MCOperand::createReg(0));
1455 } else
1456 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1457 return S;
1458 }
1459
DecodeCCOutOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1460 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1461 uint64_t Address, const void *Decoder) {
1462 if (Val)
1463 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1464 else
1465 Inst.addOperand(MCOperand::createReg(0));
1466 return MCDisassembler::Success;
1467 }
1468
DecodeSORegImmOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1469 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1470 uint64_t Address, const void *Decoder) {
1471 DecodeStatus S = MCDisassembler::Success;
1472
1473 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1474 unsigned type = fieldFromInstruction(Val, 5, 2);
1475 unsigned imm = fieldFromInstruction(Val, 7, 5);
1476
1477 // Register-immediate
1478 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1479 return MCDisassembler::Fail;
1480
1481 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1482 switch (type) {
1483 case 0:
1484 Shift = ARM_AM::lsl;
1485 break;
1486 case 1:
1487 Shift = ARM_AM::lsr;
1488 break;
1489 case 2:
1490 Shift = ARM_AM::asr;
1491 break;
1492 case 3:
1493 Shift = ARM_AM::ror;
1494 break;
1495 }
1496
1497 if (Shift == ARM_AM::ror && imm == 0)
1498 Shift = ARM_AM::rrx;
1499
1500 unsigned Op = Shift | (imm << 3);
1501 Inst.addOperand(MCOperand::createImm(Op));
1502
1503 return S;
1504 }
1505
DecodeSORegRegOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1506 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1507 uint64_t Address, const void *Decoder) {
1508 DecodeStatus S = MCDisassembler::Success;
1509
1510 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1511 unsigned type = fieldFromInstruction(Val, 5, 2);
1512 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1513
1514 // Register-register
1515 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1516 return MCDisassembler::Fail;
1517 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1518 return MCDisassembler::Fail;
1519
1520 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1521 switch (type) {
1522 case 0:
1523 Shift = ARM_AM::lsl;
1524 break;
1525 case 1:
1526 Shift = ARM_AM::lsr;
1527 break;
1528 case 2:
1529 Shift = ARM_AM::asr;
1530 break;
1531 case 3:
1532 Shift = ARM_AM::ror;
1533 break;
1534 }
1535
1536 Inst.addOperand(MCOperand::createImm(Shift));
1537
1538 return S;
1539 }
1540
DecodeRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1541 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1542 uint64_t Address, const void *Decoder) {
1543 DecodeStatus S = MCDisassembler::Success;
1544
1545 bool NeedDisjointWriteback = false;
1546 unsigned WritebackReg = 0;
1547 bool CLRM = false;
1548 switch (Inst.getOpcode()) {
1549 default:
1550 break;
1551 case ARM::LDMIA_UPD:
1552 case ARM::LDMDB_UPD:
1553 case ARM::LDMIB_UPD:
1554 case ARM::LDMDA_UPD:
1555 case ARM::t2LDMIA_UPD:
1556 case ARM::t2LDMDB_UPD:
1557 case ARM::t2STMIA_UPD:
1558 case ARM::t2STMDB_UPD:
1559 NeedDisjointWriteback = true;
1560 WritebackReg = Inst.getOperand(0).getReg();
1561 break;
1562 case ARM::t2CLRM:
1563 CLRM = true;
1564 break;
1565 }
1566
1567 // Empty register lists are not allowed.
1568 if (Val == 0) return MCDisassembler::Fail;
1569 for (unsigned i = 0; i < 16; ++i) {
1570 if (Val & (1 << i)) {
1571 if (CLRM) {
1572 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1573 return MCDisassembler::Fail;
1574 }
1575 } else {
1576 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1577 return MCDisassembler::Fail;
1578 // Writeback not allowed if Rn is in the target list.
1579 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1580 Check(S, MCDisassembler::SoftFail);
1581 }
1582 }
1583 }
1584
1585 return S;
1586 }
1587
DecodeSPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1588 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1589 uint64_t Address, const void *Decoder) {
1590 DecodeStatus S = MCDisassembler::Success;
1591
1592 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1593 unsigned regs = fieldFromInstruction(Val, 0, 8);
1594
1595 // In case of unpredictable encoding, tweak the operands.
1596 if (regs == 0 || (Vd + regs) > 32) {
1597 regs = Vd + regs > 32 ? 32 - Vd : regs;
1598 regs = std::max( 1u, regs);
1599 S = MCDisassembler::SoftFail;
1600 }
1601
1602 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1603 return MCDisassembler::Fail;
1604 for (unsigned i = 0; i < (regs - 1); ++i) {
1605 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1606 return MCDisassembler::Fail;
1607 }
1608
1609 return S;
1610 }
1611
DecodeDPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1612 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1613 uint64_t Address, const void *Decoder) {
1614 DecodeStatus S = MCDisassembler::Success;
1615
1616 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1617 unsigned regs = fieldFromInstruction(Val, 1, 7);
1618
1619 // In case of unpredictable encoding, tweak the operands.
1620 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1621 regs = Vd + regs > 32 ? 32 - Vd : regs;
1622 regs = std::max( 1u, regs);
1623 regs = std::min(16u, regs);
1624 S = MCDisassembler::SoftFail;
1625 }
1626
1627 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1628 return MCDisassembler::Fail;
1629 for (unsigned i = 0; i < (regs - 1); ++i) {
1630 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1631 return MCDisassembler::Fail;
1632 }
1633
1634 return S;
1635 }
1636
DecodeBitfieldMaskOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1637 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1638 uint64_t Address, const void *Decoder) {
1639 // This operand encodes a mask of contiguous zeros between a specified MSB
1640 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1641 // the mask of all bits LSB-and-lower, and then xor them to create
1642 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1643 // create the final mask.
1644 unsigned msb = fieldFromInstruction(Val, 5, 5);
1645 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1646
1647 DecodeStatus S = MCDisassembler::Success;
1648 if (lsb > msb) {
1649 Check(S, MCDisassembler::SoftFail);
1650 // The check above will cause the warning for the "potentially undefined
1651 // instruction encoding" but we can't build a bad MCOperand value here
1652 // with a lsb > msb or else printing the MCInst will cause a crash.
1653 lsb = msb;
1654 }
1655
1656 uint32_t msb_mask = 0xFFFFFFFF;
1657 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1658 uint32_t lsb_mask = (1U << lsb) - 1;
1659
1660 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1661 return S;
1662 }
1663
DecodeCopMemInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1664 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1665 uint64_t Address, const void *Decoder) {
1666 DecodeStatus S = MCDisassembler::Success;
1667
1668 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1669 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1670 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1671 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1672 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1673 unsigned U = fieldFromInstruction(Insn, 23, 1);
1674 const FeatureBitset &featureBits =
1675 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1676
1677 switch (Inst.getOpcode()) {
1678 case ARM::LDC_OFFSET:
1679 case ARM::LDC_PRE:
1680 case ARM::LDC_POST:
1681 case ARM::LDC_OPTION:
1682 case ARM::LDCL_OFFSET:
1683 case ARM::LDCL_PRE:
1684 case ARM::LDCL_POST:
1685 case ARM::LDCL_OPTION:
1686 case ARM::STC_OFFSET:
1687 case ARM::STC_PRE:
1688 case ARM::STC_POST:
1689 case ARM::STC_OPTION:
1690 case ARM::STCL_OFFSET:
1691 case ARM::STCL_PRE:
1692 case ARM::STCL_POST:
1693 case ARM::STCL_OPTION:
1694 case ARM::t2LDC_OFFSET:
1695 case ARM::t2LDC_PRE:
1696 case ARM::t2LDC_POST:
1697 case ARM::t2LDC_OPTION:
1698 case ARM::t2LDCL_OFFSET:
1699 case ARM::t2LDCL_PRE:
1700 case ARM::t2LDCL_POST:
1701 case ARM::t2LDCL_OPTION:
1702 case ARM::t2STC_OFFSET:
1703 case ARM::t2STC_PRE:
1704 case ARM::t2STC_POST:
1705 case ARM::t2STC_OPTION:
1706 case ARM::t2STCL_OFFSET:
1707 case ARM::t2STCL_PRE:
1708 case ARM::t2STCL_POST:
1709 case ARM::t2STCL_OPTION:
1710 case ARM::t2LDC2_OFFSET:
1711 case ARM::t2LDC2L_OFFSET:
1712 case ARM::t2LDC2_PRE:
1713 case ARM::t2LDC2L_PRE:
1714 case ARM::t2STC2_OFFSET:
1715 case ARM::t2STC2L_OFFSET:
1716 case ARM::t2STC2_PRE:
1717 case ARM::t2STC2L_PRE:
1718 case ARM::LDC2_OFFSET:
1719 case ARM::LDC2L_OFFSET:
1720 case ARM::LDC2_PRE:
1721 case ARM::LDC2L_PRE:
1722 case ARM::STC2_OFFSET:
1723 case ARM::STC2L_OFFSET:
1724 case ARM::STC2_PRE:
1725 case ARM::STC2L_PRE:
1726 case ARM::t2LDC2_OPTION:
1727 case ARM::t2STC2_OPTION:
1728 case ARM::t2LDC2_POST:
1729 case ARM::t2LDC2L_POST:
1730 case ARM::t2STC2_POST:
1731 case ARM::t2STC2L_POST:
1732 case ARM::LDC2_POST:
1733 case ARM::LDC2L_POST:
1734 case ARM::STC2_POST:
1735 case ARM::STC2L_POST:
1736 if (coproc == 0xA || coproc == 0xB ||
1737 (featureBits[ARM::HasV8_1MMainlineOps] &&
1738 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1739 coproc == 0xE || coproc == 0xF)))
1740 return MCDisassembler::Fail;
1741 break;
1742 default:
1743 break;
1744 }
1745
1746 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1747 return MCDisassembler::Fail;
1748
1749 Inst.addOperand(MCOperand::createImm(coproc));
1750 Inst.addOperand(MCOperand::createImm(CRd));
1751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1752 return MCDisassembler::Fail;
1753
1754 switch (Inst.getOpcode()) {
1755 case ARM::t2LDC2_OFFSET:
1756 case ARM::t2LDC2L_OFFSET:
1757 case ARM::t2LDC2_PRE:
1758 case ARM::t2LDC2L_PRE:
1759 case ARM::t2STC2_OFFSET:
1760 case ARM::t2STC2L_OFFSET:
1761 case ARM::t2STC2_PRE:
1762 case ARM::t2STC2L_PRE:
1763 case ARM::LDC2_OFFSET:
1764 case ARM::LDC2L_OFFSET:
1765 case ARM::LDC2_PRE:
1766 case ARM::LDC2L_PRE:
1767 case ARM::STC2_OFFSET:
1768 case ARM::STC2L_OFFSET:
1769 case ARM::STC2_PRE:
1770 case ARM::STC2L_PRE:
1771 case ARM::t2LDC_OFFSET:
1772 case ARM::t2LDCL_OFFSET:
1773 case ARM::t2LDC_PRE:
1774 case ARM::t2LDCL_PRE:
1775 case ARM::t2STC_OFFSET:
1776 case ARM::t2STCL_OFFSET:
1777 case ARM::t2STC_PRE:
1778 case ARM::t2STCL_PRE:
1779 case ARM::LDC_OFFSET:
1780 case ARM::LDCL_OFFSET:
1781 case ARM::LDC_PRE:
1782 case ARM::LDCL_PRE:
1783 case ARM::STC_OFFSET:
1784 case ARM::STCL_OFFSET:
1785 case ARM::STC_PRE:
1786 case ARM::STCL_PRE:
1787 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1788 Inst.addOperand(MCOperand::createImm(imm));
1789 break;
1790 case ARM::t2LDC2_POST:
1791 case ARM::t2LDC2L_POST:
1792 case ARM::t2STC2_POST:
1793 case ARM::t2STC2L_POST:
1794 case ARM::LDC2_POST:
1795 case ARM::LDC2L_POST:
1796 case ARM::STC2_POST:
1797 case ARM::STC2L_POST:
1798 case ARM::t2LDC_POST:
1799 case ARM::t2LDCL_POST:
1800 case ARM::t2STC_POST:
1801 case ARM::t2STCL_POST:
1802 case ARM::LDC_POST:
1803 case ARM::LDCL_POST:
1804 case ARM::STC_POST:
1805 case ARM::STCL_POST:
1806 imm |= U << 8;
1807 LLVM_FALLTHROUGH;
1808 default:
1809 // The 'option' variant doesn't encode 'U' in the immediate since
1810 // the immediate is unsigned [0,255].
1811 Inst.addOperand(MCOperand::createImm(imm));
1812 break;
1813 }
1814
1815 switch (Inst.getOpcode()) {
1816 case ARM::LDC_OFFSET:
1817 case ARM::LDC_PRE:
1818 case ARM::LDC_POST:
1819 case ARM::LDC_OPTION:
1820 case ARM::LDCL_OFFSET:
1821 case ARM::LDCL_PRE:
1822 case ARM::LDCL_POST:
1823 case ARM::LDCL_OPTION:
1824 case ARM::STC_OFFSET:
1825 case ARM::STC_PRE:
1826 case ARM::STC_POST:
1827 case ARM::STC_OPTION:
1828 case ARM::STCL_OFFSET:
1829 case ARM::STCL_PRE:
1830 case ARM::STCL_POST:
1831 case ARM::STCL_OPTION:
1832 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1833 return MCDisassembler::Fail;
1834 break;
1835 default:
1836 break;
1837 }
1838
1839 return S;
1840 }
1841
1842 static DecodeStatus
DecodeAddrMode2IdxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1843 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1844 uint64_t Address, const void *Decoder) {
1845 DecodeStatus S = MCDisassembler::Success;
1846
1847 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1848 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1849 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1850 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1851 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1852 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1853 unsigned P = fieldFromInstruction(Insn, 24, 1);
1854 unsigned W = fieldFromInstruction(Insn, 21, 1);
1855
1856 // On stores, the writeback operand precedes Rt.
1857 switch (Inst.getOpcode()) {
1858 case ARM::STR_POST_IMM:
1859 case ARM::STR_POST_REG:
1860 case ARM::STRB_POST_IMM:
1861 case ARM::STRB_POST_REG:
1862 case ARM::STRT_POST_REG:
1863 case ARM::STRT_POST_IMM:
1864 case ARM::STRBT_POST_REG:
1865 case ARM::STRBT_POST_IMM:
1866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1867 return MCDisassembler::Fail;
1868 break;
1869 default:
1870 break;
1871 }
1872
1873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1874 return MCDisassembler::Fail;
1875
1876 // On loads, the writeback operand comes after Rt.
1877 switch (Inst.getOpcode()) {
1878 case ARM::LDR_POST_IMM:
1879 case ARM::LDR_POST_REG:
1880 case ARM::LDRB_POST_IMM:
1881 case ARM::LDRB_POST_REG:
1882 case ARM::LDRBT_POST_REG:
1883 case ARM::LDRBT_POST_IMM:
1884 case ARM::LDRT_POST_REG:
1885 case ARM::LDRT_POST_IMM:
1886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1887 return MCDisassembler::Fail;
1888 break;
1889 default:
1890 break;
1891 }
1892
1893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1894 return MCDisassembler::Fail;
1895
1896 ARM_AM::AddrOpc Op = ARM_AM::add;
1897 if (!fieldFromInstruction(Insn, 23, 1))
1898 Op = ARM_AM::sub;
1899
1900 bool writeback = (P == 0) || (W == 1);
1901 unsigned idx_mode = 0;
1902 if (P && writeback)
1903 idx_mode = ARMII::IndexModePre;
1904 else if (!P && writeback)
1905 idx_mode = ARMII::IndexModePost;
1906
1907 if (writeback && (Rn == 15 || Rn == Rt))
1908 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1909
1910 if (reg) {
1911 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1912 return MCDisassembler::Fail;
1913 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1914 switch( fieldFromInstruction(Insn, 5, 2)) {
1915 case 0:
1916 Opc = ARM_AM::lsl;
1917 break;
1918 case 1:
1919 Opc = ARM_AM::lsr;
1920 break;
1921 case 2:
1922 Opc = ARM_AM::asr;
1923 break;
1924 case 3:
1925 Opc = ARM_AM::ror;
1926 break;
1927 default:
1928 return MCDisassembler::Fail;
1929 }
1930 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1931 if (Opc == ARM_AM::ror && amt == 0)
1932 Opc = ARM_AM::rrx;
1933 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1934
1935 Inst.addOperand(MCOperand::createImm(imm));
1936 } else {
1937 Inst.addOperand(MCOperand::createReg(0));
1938 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1939 Inst.addOperand(MCOperand::createImm(tmp));
1940 }
1941
1942 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1943 return MCDisassembler::Fail;
1944
1945 return S;
1946 }
1947
DecodeSORegMemOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1948 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1949 uint64_t Address, const void *Decoder) {
1950 DecodeStatus S = MCDisassembler::Success;
1951
1952 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1953 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1954 unsigned type = fieldFromInstruction(Val, 5, 2);
1955 unsigned imm = fieldFromInstruction(Val, 7, 5);
1956 unsigned U = fieldFromInstruction(Val, 12, 1);
1957
1958 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1959 switch (type) {
1960 case 0:
1961 ShOp = ARM_AM::lsl;
1962 break;
1963 case 1:
1964 ShOp = ARM_AM::lsr;
1965 break;
1966 case 2:
1967 ShOp = ARM_AM::asr;
1968 break;
1969 case 3:
1970 ShOp = ARM_AM::ror;
1971 break;
1972 }
1973
1974 if (ShOp == ARM_AM::ror && imm == 0)
1975 ShOp = ARM_AM::rrx;
1976
1977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1978 return MCDisassembler::Fail;
1979 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1980 return MCDisassembler::Fail;
1981 unsigned shift;
1982 if (U)
1983 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1984 else
1985 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1986 Inst.addOperand(MCOperand::createImm(shift));
1987
1988 return S;
1989 }
1990
1991 static DecodeStatus
DecodeAddrMode3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1992 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1993 uint64_t Address, const void *Decoder) {
1994 DecodeStatus S = MCDisassembler::Success;
1995
1996 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1997 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1998 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1999 unsigned type = fieldFromInstruction(Insn, 22, 1);
2000 unsigned imm = fieldFromInstruction(Insn, 8, 4);
2001 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
2002 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2003 unsigned W = fieldFromInstruction(Insn, 21, 1);
2004 unsigned P = fieldFromInstruction(Insn, 24, 1);
2005 unsigned Rt2 = Rt + 1;
2006
2007 bool writeback = (W == 1) | (P == 0);
2008
2009 // For {LD,ST}RD, Rt must be even, else undefined.
2010 switch (Inst.getOpcode()) {
2011 case ARM::STRD:
2012 case ARM::STRD_PRE:
2013 case ARM::STRD_POST:
2014 case ARM::LDRD:
2015 case ARM::LDRD_PRE:
2016 case ARM::LDRD_POST:
2017 if (Rt & 0x1) S = MCDisassembler::SoftFail;
2018 break;
2019 default:
2020 break;
2021 }
2022 switch (Inst.getOpcode()) {
2023 case ARM::STRD:
2024 case ARM::STRD_PRE:
2025 case ARM::STRD_POST:
2026 if (P == 0 && W == 1)
2027 S = MCDisassembler::SoftFail;
2028
2029 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2030 S = MCDisassembler::SoftFail;
2031 if (type && Rm == 15)
2032 S = MCDisassembler::SoftFail;
2033 if (Rt2 == 15)
2034 S = MCDisassembler::SoftFail;
2035 if (!type && fieldFromInstruction(Insn, 8, 4))
2036 S = MCDisassembler::SoftFail;
2037 break;
2038 case ARM::STRH:
2039 case ARM::STRH_PRE:
2040 case ARM::STRH_POST:
2041 if (Rt == 15)
2042 S = MCDisassembler::SoftFail;
2043 if (writeback && (Rn == 15 || Rn == Rt))
2044 S = MCDisassembler::SoftFail;
2045 if (!type && Rm == 15)
2046 S = MCDisassembler::SoftFail;
2047 break;
2048 case ARM::LDRD:
2049 case ARM::LDRD_PRE:
2050 case ARM::LDRD_POST:
2051 if (type && Rn == 15) {
2052 if (Rt2 == 15)
2053 S = MCDisassembler::SoftFail;
2054 break;
2055 }
2056 if (P == 0 && W == 1)
2057 S = MCDisassembler::SoftFail;
2058 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2059 S = MCDisassembler::SoftFail;
2060 if (!type && writeback && Rn == 15)
2061 S = MCDisassembler::SoftFail;
2062 if (writeback && (Rn == Rt || Rn == Rt2))
2063 S = MCDisassembler::SoftFail;
2064 break;
2065 case ARM::LDRH:
2066 case ARM::LDRH_PRE:
2067 case ARM::LDRH_POST:
2068 if (type && Rn == 15) {
2069 if (Rt == 15)
2070 S = MCDisassembler::SoftFail;
2071 break;
2072 }
2073 if (Rt == 15)
2074 S = MCDisassembler::SoftFail;
2075 if (!type && Rm == 15)
2076 S = MCDisassembler::SoftFail;
2077 if (!type && writeback && (Rn == 15 || Rn == Rt))
2078 S = MCDisassembler::SoftFail;
2079 break;
2080 case ARM::LDRSH:
2081 case ARM::LDRSH_PRE:
2082 case ARM::LDRSH_POST:
2083 case ARM::LDRSB:
2084 case ARM::LDRSB_PRE:
2085 case ARM::LDRSB_POST:
2086 if (type && Rn == 15) {
2087 if (Rt == 15)
2088 S = MCDisassembler::SoftFail;
2089 break;
2090 }
2091 if (type && (Rt == 15 || (writeback && Rn == Rt)))
2092 S = MCDisassembler::SoftFail;
2093 if (!type && (Rt == 15 || Rm == 15))
2094 S = MCDisassembler::SoftFail;
2095 if (!type && writeback && (Rn == 15 || Rn == Rt))
2096 S = MCDisassembler::SoftFail;
2097 break;
2098 default:
2099 break;
2100 }
2101
2102 if (writeback) { // Writeback
2103 if (P)
2104 U |= ARMII::IndexModePre << 9;
2105 else
2106 U |= ARMII::IndexModePost << 9;
2107
2108 // On stores, the writeback operand precedes Rt.
2109 switch (Inst.getOpcode()) {
2110 case ARM::STRD:
2111 case ARM::STRD_PRE:
2112 case ARM::STRD_POST:
2113 case ARM::STRH:
2114 case ARM::STRH_PRE:
2115 case ARM::STRH_POST:
2116 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2117 return MCDisassembler::Fail;
2118 break;
2119 default:
2120 break;
2121 }
2122 }
2123
2124 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2125 return MCDisassembler::Fail;
2126 switch (Inst.getOpcode()) {
2127 case ARM::STRD:
2128 case ARM::STRD_PRE:
2129 case ARM::STRD_POST:
2130 case ARM::LDRD:
2131 case ARM::LDRD_PRE:
2132 case ARM::LDRD_POST:
2133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2134 return MCDisassembler::Fail;
2135 break;
2136 default:
2137 break;
2138 }
2139
2140 if (writeback) {
2141 // On loads, the writeback operand comes after Rt.
2142 switch (Inst.getOpcode()) {
2143 case ARM::LDRD:
2144 case ARM::LDRD_PRE:
2145 case ARM::LDRD_POST:
2146 case ARM::LDRH:
2147 case ARM::LDRH_PRE:
2148 case ARM::LDRH_POST:
2149 case ARM::LDRSH:
2150 case ARM::LDRSH_PRE:
2151 case ARM::LDRSH_POST:
2152 case ARM::LDRSB:
2153 case ARM::LDRSB_PRE:
2154 case ARM::LDRSB_POST:
2155 case ARM::LDRHTr:
2156 case ARM::LDRSBTr:
2157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2158 return MCDisassembler::Fail;
2159 break;
2160 default:
2161 break;
2162 }
2163 }
2164
2165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2166 return MCDisassembler::Fail;
2167
2168 if (type) {
2169 Inst.addOperand(MCOperand::createReg(0));
2170 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2171 } else {
2172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2173 return MCDisassembler::Fail;
2174 Inst.addOperand(MCOperand::createImm(U));
2175 }
2176
2177 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2178 return MCDisassembler::Fail;
2179
2180 return S;
2181 }
2182
DecodeRFEInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2183 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
2184 uint64_t Address, const void *Decoder) {
2185 DecodeStatus S = MCDisassembler::Success;
2186
2187 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2188 unsigned mode = fieldFromInstruction(Insn, 23, 2);
2189
2190 switch (mode) {
2191 case 0:
2192 mode = ARM_AM::da;
2193 break;
2194 case 1:
2195 mode = ARM_AM::ia;
2196 break;
2197 case 2:
2198 mode = ARM_AM::db;
2199 break;
2200 case 3:
2201 mode = ARM_AM::ib;
2202 break;
2203 }
2204
2205 Inst.addOperand(MCOperand::createImm(mode));
2206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2207 return MCDisassembler::Fail;
2208
2209 return S;
2210 }
2211
DecodeQADDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2212 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
2213 uint64_t Address, const void *Decoder) {
2214 DecodeStatus S = MCDisassembler::Success;
2215
2216 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2217 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2218 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2219 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2220
2221 if (pred == 0xF)
2222 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2223
2224 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2225 return MCDisassembler::Fail;
2226 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2227 return MCDisassembler::Fail;
2228 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2229 return MCDisassembler::Fail;
2230 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2231 return MCDisassembler::Fail;
2232 return S;
2233 }
2234
DecodeMemMultipleWritebackInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2235 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
2236 unsigned Insn,
2237 uint64_t Address, const void *Decoder) {
2238 DecodeStatus S = MCDisassembler::Success;
2239
2240 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2241 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2242 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2243
2244 if (pred == 0xF) {
2245 // Ambiguous with RFE and SRS
2246 switch (Inst.getOpcode()) {
2247 case ARM::LDMDA:
2248 Inst.setOpcode(ARM::RFEDA);
2249 break;
2250 case ARM::LDMDA_UPD:
2251 Inst.setOpcode(ARM::RFEDA_UPD);
2252 break;
2253 case ARM::LDMDB:
2254 Inst.setOpcode(ARM::RFEDB);
2255 break;
2256 case ARM::LDMDB_UPD:
2257 Inst.setOpcode(ARM::RFEDB_UPD);
2258 break;
2259 case ARM::LDMIA:
2260 Inst.setOpcode(ARM::RFEIA);
2261 break;
2262 case ARM::LDMIA_UPD:
2263 Inst.setOpcode(ARM::RFEIA_UPD);
2264 break;
2265 case ARM::LDMIB:
2266 Inst.setOpcode(ARM::RFEIB);
2267 break;
2268 case ARM::LDMIB_UPD:
2269 Inst.setOpcode(ARM::RFEIB_UPD);
2270 break;
2271 case ARM::STMDA:
2272 Inst.setOpcode(ARM::SRSDA);
2273 break;
2274 case ARM::STMDA_UPD:
2275 Inst.setOpcode(ARM::SRSDA_UPD);
2276 break;
2277 case ARM::STMDB:
2278 Inst.setOpcode(ARM::SRSDB);
2279 break;
2280 case ARM::STMDB_UPD:
2281 Inst.setOpcode(ARM::SRSDB_UPD);
2282 break;
2283 case ARM::STMIA:
2284 Inst.setOpcode(ARM::SRSIA);
2285 break;
2286 case ARM::STMIA_UPD:
2287 Inst.setOpcode(ARM::SRSIA_UPD);
2288 break;
2289 case ARM::STMIB:
2290 Inst.setOpcode(ARM::SRSIB);
2291 break;
2292 case ARM::STMIB_UPD:
2293 Inst.setOpcode(ARM::SRSIB_UPD);
2294 break;
2295 default:
2296 return MCDisassembler::Fail;
2297 }
2298
2299 // For stores (which become SRS's, the only operand is the mode.
2300 if (fieldFromInstruction(Insn, 20, 1) == 0) {
2301 // Check SRS encoding constraints
2302 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2303 fieldFromInstruction(Insn, 20, 1) == 0))
2304 return MCDisassembler::Fail;
2305
2306 Inst.addOperand(
2307 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
2308 return S;
2309 }
2310
2311 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2312 }
2313
2314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2315 return MCDisassembler::Fail;
2316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2317 return MCDisassembler::Fail; // Tied
2318 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2319 return MCDisassembler::Fail;
2320 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2321 return MCDisassembler::Fail;
2322
2323 return S;
2324 }
2325
2326 // Check for UNPREDICTABLE predicated ESB instruction
DecodeHINTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2327 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
2328 uint64_t Address, const void *Decoder) {
2329 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2330 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2331 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2332 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2333
2334 DecodeStatus S = MCDisassembler::Success;
2335
2336 Inst.addOperand(MCOperand::createImm(imm8));
2337
2338 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2339 return MCDisassembler::Fail;
2340
2341 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2342 // so all predicates should be allowed.
2343 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2344 S = MCDisassembler::SoftFail;
2345
2346 return S;
2347 }
2348
DecodeCPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2349 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
2350 uint64_t Address, const void *Decoder) {
2351 unsigned imod = fieldFromInstruction(Insn, 18, 2);
2352 unsigned M = fieldFromInstruction(Insn, 17, 1);
2353 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2354 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2355
2356 DecodeStatus S = MCDisassembler::Success;
2357
2358 // This decoder is called from multiple location that do not check
2359 // the full encoding is valid before they do.
2360 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2361 fieldFromInstruction(Insn, 16, 1) != 0 ||
2362 fieldFromInstruction(Insn, 20, 8) != 0x10)
2363 return MCDisassembler::Fail;
2364
2365 // imod == '01' --> UNPREDICTABLE
2366 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2367 // return failure here. The '01' imod value is unprintable, so there's
2368 // nothing useful we could do even if we returned UNPREDICTABLE.
2369
2370 if (imod == 1) return MCDisassembler::Fail;
2371
2372 if (imod && M) {
2373 Inst.setOpcode(ARM::CPS3p);
2374 Inst.addOperand(MCOperand::createImm(imod));
2375 Inst.addOperand(MCOperand::createImm(iflags));
2376 Inst.addOperand(MCOperand::createImm(mode));
2377 } else if (imod && !M) {
2378 Inst.setOpcode(ARM::CPS2p);
2379 Inst.addOperand(MCOperand::createImm(imod));
2380 Inst.addOperand(MCOperand::createImm(iflags));
2381 if (mode) S = MCDisassembler::SoftFail;
2382 } else if (!imod && M) {
2383 Inst.setOpcode(ARM::CPS1p);
2384 Inst.addOperand(MCOperand::createImm(mode));
2385 if (iflags) S = MCDisassembler::SoftFail;
2386 } else {
2387 // imod == '00' && M == '0' --> UNPREDICTABLE
2388 Inst.setOpcode(ARM::CPS1p);
2389 Inst.addOperand(MCOperand::createImm(mode));
2390 S = MCDisassembler::SoftFail;
2391 }
2392
2393 return S;
2394 }
2395
DecodeT2CPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2396 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2397 uint64_t Address, const void *Decoder) {
2398 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2399 unsigned M = fieldFromInstruction(Insn, 8, 1);
2400 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2401 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2402
2403 DecodeStatus S = MCDisassembler::Success;
2404
2405 // imod == '01' --> UNPREDICTABLE
2406 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2407 // return failure here. The '01' imod value is unprintable, so there's
2408 // nothing useful we could do even if we returned UNPREDICTABLE.
2409
2410 if (imod == 1) return MCDisassembler::Fail;
2411
2412 if (imod && M) {
2413 Inst.setOpcode(ARM::t2CPS3p);
2414 Inst.addOperand(MCOperand::createImm(imod));
2415 Inst.addOperand(MCOperand::createImm(iflags));
2416 Inst.addOperand(MCOperand::createImm(mode));
2417 } else if (imod && !M) {
2418 Inst.setOpcode(ARM::t2CPS2p);
2419 Inst.addOperand(MCOperand::createImm(imod));
2420 Inst.addOperand(MCOperand::createImm(iflags));
2421 if (mode) S = MCDisassembler::SoftFail;
2422 } else if (!imod && M) {
2423 Inst.setOpcode(ARM::t2CPS1p);
2424 Inst.addOperand(MCOperand::createImm(mode));
2425 if (iflags) S = MCDisassembler::SoftFail;
2426 } else {
2427 // imod == '00' && M == '0' --> this is a HINT instruction
2428 int imm = fieldFromInstruction(Insn, 0, 8);
2429 // HINT are defined only for immediate in [0..4]
2430 if(imm > 4) return MCDisassembler::Fail;
2431 Inst.setOpcode(ARM::t2HINT);
2432 Inst.addOperand(MCOperand::createImm(imm));
2433 }
2434
2435 return S;
2436 }
2437
DecodeT2MOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2438 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2439 uint64_t Address, const void *Decoder) {
2440 DecodeStatus S = MCDisassembler::Success;
2441
2442 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2443 unsigned imm = 0;
2444
2445 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2446 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2447 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2448 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2449
2450 if (Inst.getOpcode() == ARM::t2MOVTi16)
2451 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2452 return MCDisassembler::Fail;
2453 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2454 return MCDisassembler::Fail;
2455
2456 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2457 Inst.addOperand(MCOperand::createImm(imm));
2458
2459 return S;
2460 }
2461
DecodeArmMOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2462 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2463 uint64_t Address, const void *Decoder) {
2464 DecodeStatus S = MCDisassembler::Success;
2465
2466 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2467 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2468 unsigned imm = 0;
2469
2470 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2471 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2472
2473 if (Inst.getOpcode() == ARM::MOVTi16)
2474 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2475 return MCDisassembler::Fail;
2476
2477 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2478 return MCDisassembler::Fail;
2479
2480 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2481 Inst.addOperand(MCOperand::createImm(imm));
2482
2483 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2484 return MCDisassembler::Fail;
2485
2486 return S;
2487 }
2488
DecodeSMLAInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2489 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2490 uint64_t Address, const void *Decoder) {
2491 DecodeStatus S = MCDisassembler::Success;
2492
2493 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2494 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2495 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2496 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2497 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2498
2499 if (pred == 0xF)
2500 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2501
2502 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2503 return MCDisassembler::Fail;
2504 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2505 return MCDisassembler::Fail;
2506 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2507 return MCDisassembler::Fail;
2508 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2509 return MCDisassembler::Fail;
2510
2511 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2512 return MCDisassembler::Fail;
2513
2514 return S;
2515 }
2516
DecodeTSTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2517 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2518 uint64_t Address, const void *Decoder) {
2519 DecodeStatus S = MCDisassembler::Success;
2520
2521 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2522 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2523 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2524
2525 if (Pred == 0xF)
2526 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2527
2528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2529 return MCDisassembler::Fail;
2530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2531 return MCDisassembler::Fail;
2532 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2533 return MCDisassembler::Fail;
2534
2535 return S;
2536 }
2537
DecodeSETPANInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2538 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2539 uint64_t Address, const void *Decoder) {
2540 DecodeStatus S = MCDisassembler::Success;
2541
2542 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2543
2544 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2545 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2546
2547 if (!FeatureBits[ARM::HasV8_1aOps] ||
2548 !FeatureBits[ARM::HasV8Ops])
2549 return MCDisassembler::Fail;
2550
2551 // Decoder can be called from DecodeTST, which does not check the full
2552 // encoding is valid.
2553 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2554 fieldFromInstruction(Insn, 4,4) != 0)
2555 return MCDisassembler::Fail;
2556 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2557 fieldFromInstruction(Insn, 0,4) != 0)
2558 S = MCDisassembler::SoftFail;
2559
2560 Inst.setOpcode(ARM::SETPAN);
2561 Inst.addOperand(MCOperand::createImm(Imm));
2562
2563 return S;
2564 }
2565
DecodeAddrModeImm12Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2566 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2567 uint64_t Address, const void *Decoder) {
2568 DecodeStatus S = MCDisassembler::Success;
2569
2570 unsigned add = fieldFromInstruction(Val, 12, 1);
2571 unsigned imm = fieldFromInstruction(Val, 0, 12);
2572 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2573
2574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2575 return MCDisassembler::Fail;
2576
2577 if (!add) imm *= -1;
2578 if (imm == 0 && !add) imm = INT32_MIN;
2579 Inst.addOperand(MCOperand::createImm(imm));
2580 if (Rn == 15)
2581 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2582
2583 return S;
2584 }
2585
DecodeAddrMode5Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2586 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2587 uint64_t Address, const void *Decoder) {
2588 DecodeStatus S = MCDisassembler::Success;
2589
2590 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2591 // U == 1 to add imm, 0 to subtract it.
2592 unsigned U = fieldFromInstruction(Val, 8, 1);
2593 unsigned imm = fieldFromInstruction(Val, 0, 8);
2594
2595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2596 return MCDisassembler::Fail;
2597
2598 if (U)
2599 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2600 else
2601 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2602
2603 return S;
2604 }
2605
DecodeAddrMode5FP16Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2606 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2607 uint64_t Address, const void *Decoder) {
2608 DecodeStatus S = MCDisassembler::Success;
2609
2610 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2611 // U == 1 to add imm, 0 to subtract it.
2612 unsigned U = fieldFromInstruction(Val, 8, 1);
2613 unsigned imm = fieldFromInstruction(Val, 0, 8);
2614
2615 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2616 return MCDisassembler::Fail;
2617
2618 if (U)
2619 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2620 else
2621 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2622
2623 return S;
2624 }
2625
DecodeAddrMode7Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2626 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2627 uint64_t Address, const void *Decoder) {
2628 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2629 }
2630
2631 static DecodeStatus
DecodeT2BInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2632 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2633 uint64_t Address, const void *Decoder) {
2634 DecodeStatus Status = MCDisassembler::Success;
2635
2636 // Note the J1 and J2 values are from the encoded instruction. So here
2637 // change them to I1 and I2 values via as documented:
2638 // I1 = NOT(J1 EOR S);
2639 // I2 = NOT(J2 EOR S);
2640 // and build the imm32 with one trailing zero as documented:
2641 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2642 unsigned S = fieldFromInstruction(Insn, 26, 1);
2643 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2644 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2645 unsigned I1 = !(J1 ^ S);
2646 unsigned I2 = !(J2 ^ S);
2647 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2648 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2649 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2650 int imm32 = SignExtend32<25>(tmp << 1);
2651 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2652 true, 4, Inst, Decoder))
2653 Inst.addOperand(MCOperand::createImm(imm32));
2654
2655 return Status;
2656 }
2657
2658 static DecodeStatus
DecodeBranchImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2659 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2660 uint64_t Address, const void *Decoder) {
2661 DecodeStatus S = MCDisassembler::Success;
2662
2663 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2664 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2665
2666 if (pred == 0xF) {
2667 Inst.setOpcode(ARM::BLXi);
2668 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2669 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2670 true, 4, Inst, Decoder))
2671 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2672 return S;
2673 }
2674
2675 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2676 true, 4, Inst, Decoder))
2677 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2678 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2679 return MCDisassembler::Fail;
2680
2681 return S;
2682 }
2683
DecodeAddrMode6Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2684 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2685 uint64_t Address, const void *Decoder) {
2686 DecodeStatus S = MCDisassembler::Success;
2687
2688 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2689 unsigned align = fieldFromInstruction(Val, 4, 2);
2690
2691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2692 return MCDisassembler::Fail;
2693 if (!align)
2694 Inst.addOperand(MCOperand::createImm(0));
2695 else
2696 Inst.addOperand(MCOperand::createImm(4 << align));
2697
2698 return S;
2699 }
2700
DecodeVLDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2701 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2702 uint64_t Address, const void *Decoder) {
2703 DecodeStatus S = MCDisassembler::Success;
2704
2705 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2706 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2707 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2708 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2709 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2710 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2711
2712 // First output register
2713 switch (Inst.getOpcode()) {
2714 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2715 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2716 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2717 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2718 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2719 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2720 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2721 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2722 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2723 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2724 return MCDisassembler::Fail;
2725 break;
2726 case ARM::VLD2b16:
2727 case ARM::VLD2b32:
2728 case ARM::VLD2b8:
2729 case ARM::VLD2b16wb_fixed:
2730 case ARM::VLD2b16wb_register:
2731 case ARM::VLD2b32wb_fixed:
2732 case ARM::VLD2b32wb_register:
2733 case ARM::VLD2b8wb_fixed:
2734 case ARM::VLD2b8wb_register:
2735 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2736 return MCDisassembler::Fail;
2737 break;
2738 default:
2739 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2740 return MCDisassembler::Fail;
2741 }
2742
2743 // Second output register
2744 switch (Inst.getOpcode()) {
2745 case ARM::VLD3d8:
2746 case ARM::VLD3d16:
2747 case ARM::VLD3d32:
2748 case ARM::VLD3d8_UPD:
2749 case ARM::VLD3d16_UPD:
2750 case ARM::VLD3d32_UPD:
2751 case ARM::VLD4d8:
2752 case ARM::VLD4d16:
2753 case ARM::VLD4d32:
2754 case ARM::VLD4d8_UPD:
2755 case ARM::VLD4d16_UPD:
2756 case ARM::VLD4d32_UPD:
2757 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2758 return MCDisassembler::Fail;
2759 break;
2760 case ARM::VLD3q8:
2761 case ARM::VLD3q16:
2762 case ARM::VLD3q32:
2763 case ARM::VLD3q8_UPD:
2764 case ARM::VLD3q16_UPD:
2765 case ARM::VLD3q32_UPD:
2766 case ARM::VLD4q8:
2767 case ARM::VLD4q16:
2768 case ARM::VLD4q32:
2769 case ARM::VLD4q8_UPD:
2770 case ARM::VLD4q16_UPD:
2771 case ARM::VLD4q32_UPD:
2772 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2773 return MCDisassembler::Fail;
2774 break;
2775 default:
2776 break;
2777 }
2778
2779 // Third output register
2780 switch(Inst.getOpcode()) {
2781 case ARM::VLD3d8:
2782 case ARM::VLD3d16:
2783 case ARM::VLD3d32:
2784 case ARM::VLD3d8_UPD:
2785 case ARM::VLD3d16_UPD:
2786 case ARM::VLD3d32_UPD:
2787 case ARM::VLD4d8:
2788 case ARM::VLD4d16:
2789 case ARM::VLD4d32:
2790 case ARM::VLD4d8_UPD:
2791 case ARM::VLD4d16_UPD:
2792 case ARM::VLD4d32_UPD:
2793 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2794 return MCDisassembler::Fail;
2795 break;
2796 case ARM::VLD3q8:
2797 case ARM::VLD3q16:
2798 case ARM::VLD3q32:
2799 case ARM::VLD3q8_UPD:
2800 case ARM::VLD3q16_UPD:
2801 case ARM::VLD3q32_UPD:
2802 case ARM::VLD4q8:
2803 case ARM::VLD4q16:
2804 case ARM::VLD4q32:
2805 case ARM::VLD4q8_UPD:
2806 case ARM::VLD4q16_UPD:
2807 case ARM::VLD4q32_UPD:
2808 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2809 return MCDisassembler::Fail;
2810 break;
2811 default:
2812 break;
2813 }
2814
2815 // Fourth output register
2816 switch (Inst.getOpcode()) {
2817 case ARM::VLD4d8:
2818 case ARM::VLD4d16:
2819 case ARM::VLD4d32:
2820 case ARM::VLD4d8_UPD:
2821 case ARM::VLD4d16_UPD:
2822 case ARM::VLD4d32_UPD:
2823 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2824 return MCDisassembler::Fail;
2825 break;
2826 case ARM::VLD4q8:
2827 case ARM::VLD4q16:
2828 case ARM::VLD4q32:
2829 case ARM::VLD4q8_UPD:
2830 case ARM::VLD4q16_UPD:
2831 case ARM::VLD4q32_UPD:
2832 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2833 return MCDisassembler::Fail;
2834 break;
2835 default:
2836 break;
2837 }
2838
2839 // Writeback operand
2840 switch (Inst.getOpcode()) {
2841 case ARM::VLD1d8wb_fixed:
2842 case ARM::VLD1d16wb_fixed:
2843 case ARM::VLD1d32wb_fixed:
2844 case ARM::VLD1d64wb_fixed:
2845 case ARM::VLD1d8wb_register:
2846 case ARM::VLD1d16wb_register:
2847 case ARM::VLD1d32wb_register:
2848 case ARM::VLD1d64wb_register:
2849 case ARM::VLD1q8wb_fixed:
2850 case ARM::VLD1q16wb_fixed:
2851 case ARM::VLD1q32wb_fixed:
2852 case ARM::VLD1q64wb_fixed:
2853 case ARM::VLD1q8wb_register:
2854 case ARM::VLD1q16wb_register:
2855 case ARM::VLD1q32wb_register:
2856 case ARM::VLD1q64wb_register:
2857 case ARM::VLD1d8Twb_fixed:
2858 case ARM::VLD1d8Twb_register:
2859 case ARM::VLD1d16Twb_fixed:
2860 case ARM::VLD1d16Twb_register:
2861 case ARM::VLD1d32Twb_fixed:
2862 case ARM::VLD1d32Twb_register:
2863 case ARM::VLD1d64Twb_fixed:
2864 case ARM::VLD1d64Twb_register:
2865 case ARM::VLD1d8Qwb_fixed:
2866 case ARM::VLD1d8Qwb_register:
2867 case ARM::VLD1d16Qwb_fixed:
2868 case ARM::VLD1d16Qwb_register:
2869 case ARM::VLD1d32Qwb_fixed:
2870 case ARM::VLD1d32Qwb_register:
2871 case ARM::VLD1d64Qwb_fixed:
2872 case ARM::VLD1d64Qwb_register:
2873 case ARM::VLD2d8wb_fixed:
2874 case ARM::VLD2d16wb_fixed:
2875 case ARM::VLD2d32wb_fixed:
2876 case ARM::VLD2q8wb_fixed:
2877 case ARM::VLD2q16wb_fixed:
2878 case ARM::VLD2q32wb_fixed:
2879 case ARM::VLD2d8wb_register:
2880 case ARM::VLD2d16wb_register:
2881 case ARM::VLD2d32wb_register:
2882 case ARM::VLD2q8wb_register:
2883 case ARM::VLD2q16wb_register:
2884 case ARM::VLD2q32wb_register:
2885 case ARM::VLD2b8wb_fixed:
2886 case ARM::VLD2b16wb_fixed:
2887 case ARM::VLD2b32wb_fixed:
2888 case ARM::VLD2b8wb_register:
2889 case ARM::VLD2b16wb_register:
2890 case ARM::VLD2b32wb_register:
2891 Inst.addOperand(MCOperand::createImm(0));
2892 break;
2893 case ARM::VLD3d8_UPD:
2894 case ARM::VLD3d16_UPD:
2895 case ARM::VLD3d32_UPD:
2896 case ARM::VLD3q8_UPD:
2897 case ARM::VLD3q16_UPD:
2898 case ARM::VLD3q32_UPD:
2899 case ARM::VLD4d8_UPD:
2900 case ARM::VLD4d16_UPD:
2901 case ARM::VLD4d32_UPD:
2902 case ARM::VLD4q8_UPD:
2903 case ARM::VLD4q16_UPD:
2904 case ARM::VLD4q32_UPD:
2905 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2906 return MCDisassembler::Fail;
2907 break;
2908 default:
2909 break;
2910 }
2911
2912 // AddrMode6 Base (register+alignment)
2913 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2914 return MCDisassembler::Fail;
2915
2916 // AddrMode6 Offset (register)
2917 switch (Inst.getOpcode()) {
2918 default:
2919 // The below have been updated to have explicit am6offset split
2920 // between fixed and register offset. For those instructions not
2921 // yet updated, we need to add an additional reg0 operand for the
2922 // fixed variant.
2923 //
2924 // The fixed offset encodes as Rm == 0xd, so we check for that.
2925 if (Rm == 0xd) {
2926 Inst.addOperand(MCOperand::createReg(0));
2927 break;
2928 }
2929 // Fall through to handle the register offset variant.
2930 LLVM_FALLTHROUGH;
2931 case ARM::VLD1d8wb_fixed:
2932 case ARM::VLD1d16wb_fixed:
2933 case ARM::VLD1d32wb_fixed:
2934 case ARM::VLD1d64wb_fixed:
2935 case ARM::VLD1d8Twb_fixed:
2936 case ARM::VLD1d16Twb_fixed:
2937 case ARM::VLD1d32Twb_fixed:
2938 case ARM::VLD1d64Twb_fixed:
2939 case ARM::VLD1d8Qwb_fixed:
2940 case ARM::VLD1d16Qwb_fixed:
2941 case ARM::VLD1d32Qwb_fixed:
2942 case ARM::VLD1d64Qwb_fixed:
2943 case ARM::VLD1d8wb_register:
2944 case ARM::VLD1d16wb_register:
2945 case ARM::VLD1d32wb_register:
2946 case ARM::VLD1d64wb_register:
2947 case ARM::VLD1q8wb_fixed:
2948 case ARM::VLD1q16wb_fixed:
2949 case ARM::VLD1q32wb_fixed:
2950 case ARM::VLD1q64wb_fixed:
2951 case ARM::VLD1q8wb_register:
2952 case ARM::VLD1q16wb_register:
2953 case ARM::VLD1q32wb_register:
2954 case ARM::VLD1q64wb_register:
2955 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2956 // variant encodes Rm == 0xf. Anything else is a register offset post-
2957 // increment and we need to add the register operand to the instruction.
2958 if (Rm != 0xD && Rm != 0xF &&
2959 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2960 return MCDisassembler::Fail;
2961 break;
2962 case ARM::VLD2d8wb_fixed:
2963 case ARM::VLD2d16wb_fixed:
2964 case ARM::VLD2d32wb_fixed:
2965 case ARM::VLD2b8wb_fixed:
2966 case ARM::VLD2b16wb_fixed:
2967 case ARM::VLD2b32wb_fixed:
2968 case ARM::VLD2q8wb_fixed:
2969 case ARM::VLD2q16wb_fixed:
2970 case ARM::VLD2q32wb_fixed:
2971 break;
2972 }
2973
2974 return S;
2975 }
2976
DecodeVLDST1Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2977 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2978 uint64_t Address, const void *Decoder) {
2979 unsigned type = fieldFromInstruction(Insn, 8, 4);
2980 unsigned align = fieldFromInstruction(Insn, 4, 2);
2981 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2982 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2983 if (type == 10 && align == 3) return MCDisassembler::Fail;
2984
2985 unsigned load = fieldFromInstruction(Insn, 21, 1);
2986 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2987 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2988 }
2989
DecodeVLDST2Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2990 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2991 uint64_t Address, const void *Decoder) {
2992 unsigned size = fieldFromInstruction(Insn, 6, 2);
2993 if (size == 3) return MCDisassembler::Fail;
2994
2995 unsigned type = fieldFromInstruction(Insn, 8, 4);
2996 unsigned align = fieldFromInstruction(Insn, 4, 2);
2997 if (type == 8 && align == 3) return MCDisassembler::Fail;
2998 if (type == 9 && align == 3) return MCDisassembler::Fail;
2999
3000 unsigned load = fieldFromInstruction(Insn, 21, 1);
3001 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3002 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3003 }
3004
DecodeVLDST3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3005 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
3006 uint64_t Address, const void *Decoder) {
3007 unsigned size = fieldFromInstruction(Insn, 6, 2);
3008 if (size == 3) return MCDisassembler::Fail;
3009
3010 unsigned align = fieldFromInstruction(Insn, 4, 2);
3011 if (align & 2) return MCDisassembler::Fail;
3012
3013 unsigned load = fieldFromInstruction(Insn, 21, 1);
3014 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3015 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3016 }
3017
DecodeVLDST4Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3018 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
3019 uint64_t Address, const void *Decoder) {
3020 unsigned size = fieldFromInstruction(Insn, 6, 2);
3021 if (size == 3) return MCDisassembler::Fail;
3022
3023 unsigned load = fieldFromInstruction(Insn, 21, 1);
3024 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3025 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3026 }
3027
DecodeVSTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3028 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
3029 uint64_t Address, const void *Decoder) {
3030 DecodeStatus S = MCDisassembler::Success;
3031
3032 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3033 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3034 unsigned wb = fieldFromInstruction(Insn, 16, 4);
3035 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3036 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3037 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3038
3039 // Writeback Operand
3040 switch (Inst.getOpcode()) {
3041 case ARM::VST1d8wb_fixed:
3042 case ARM::VST1d16wb_fixed:
3043 case ARM::VST1d32wb_fixed:
3044 case ARM::VST1d64wb_fixed:
3045 case ARM::VST1d8wb_register:
3046 case ARM::VST1d16wb_register:
3047 case ARM::VST1d32wb_register:
3048 case ARM::VST1d64wb_register:
3049 case ARM::VST1q8wb_fixed:
3050 case ARM::VST1q16wb_fixed:
3051 case ARM::VST1q32wb_fixed:
3052 case ARM::VST1q64wb_fixed:
3053 case ARM::VST1q8wb_register:
3054 case ARM::VST1q16wb_register:
3055 case ARM::VST1q32wb_register:
3056 case ARM::VST1q64wb_register:
3057 case ARM::VST1d8Twb_fixed:
3058 case ARM::VST1d16Twb_fixed:
3059 case ARM::VST1d32Twb_fixed:
3060 case ARM::VST1d64Twb_fixed:
3061 case ARM::VST1d8Twb_register:
3062 case ARM::VST1d16Twb_register:
3063 case ARM::VST1d32Twb_register:
3064 case ARM::VST1d64Twb_register:
3065 case ARM::VST1d8Qwb_fixed:
3066 case ARM::VST1d16Qwb_fixed:
3067 case ARM::VST1d32Qwb_fixed:
3068 case ARM::VST1d64Qwb_fixed:
3069 case ARM::VST1d8Qwb_register:
3070 case ARM::VST1d16Qwb_register:
3071 case ARM::VST1d32Qwb_register:
3072 case ARM::VST1d64Qwb_register:
3073 case ARM::VST2d8wb_fixed:
3074 case ARM::VST2d16wb_fixed:
3075 case ARM::VST2d32wb_fixed:
3076 case ARM::VST2d8wb_register:
3077 case ARM::VST2d16wb_register:
3078 case ARM::VST2d32wb_register:
3079 case ARM::VST2q8wb_fixed:
3080 case ARM::VST2q16wb_fixed:
3081 case ARM::VST2q32wb_fixed:
3082 case ARM::VST2q8wb_register:
3083 case ARM::VST2q16wb_register:
3084 case ARM::VST2q32wb_register:
3085 case ARM::VST2b8wb_fixed:
3086 case ARM::VST2b16wb_fixed:
3087 case ARM::VST2b32wb_fixed:
3088 case ARM::VST2b8wb_register:
3089 case ARM::VST2b16wb_register:
3090 case ARM::VST2b32wb_register:
3091 if (Rm == 0xF)
3092 return MCDisassembler::Fail;
3093 Inst.addOperand(MCOperand::createImm(0));
3094 break;
3095 case ARM::VST3d8_UPD:
3096 case ARM::VST3d16_UPD:
3097 case ARM::VST3d32_UPD:
3098 case ARM::VST3q8_UPD:
3099 case ARM::VST3q16_UPD:
3100 case ARM::VST3q32_UPD:
3101 case ARM::VST4d8_UPD:
3102 case ARM::VST4d16_UPD:
3103 case ARM::VST4d32_UPD:
3104 case ARM::VST4q8_UPD:
3105 case ARM::VST4q16_UPD:
3106 case ARM::VST4q32_UPD:
3107 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3108 return MCDisassembler::Fail;
3109 break;
3110 default:
3111 break;
3112 }
3113
3114 // AddrMode6 Base (register+alignment)
3115 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3116 return MCDisassembler::Fail;
3117
3118 // AddrMode6 Offset (register)
3119 switch (Inst.getOpcode()) {
3120 default:
3121 if (Rm == 0xD)
3122 Inst.addOperand(MCOperand::createReg(0));
3123 else if (Rm != 0xF) {
3124 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3125 return MCDisassembler::Fail;
3126 }
3127 break;
3128 case ARM::VST1d8wb_fixed:
3129 case ARM::VST1d16wb_fixed:
3130 case ARM::VST1d32wb_fixed:
3131 case ARM::VST1d64wb_fixed:
3132 case ARM::VST1q8wb_fixed:
3133 case ARM::VST1q16wb_fixed:
3134 case ARM::VST1q32wb_fixed:
3135 case ARM::VST1q64wb_fixed:
3136 case ARM::VST1d8Twb_fixed:
3137 case ARM::VST1d16Twb_fixed:
3138 case ARM::VST1d32Twb_fixed:
3139 case ARM::VST1d64Twb_fixed:
3140 case ARM::VST1d8Qwb_fixed:
3141 case ARM::VST1d16Qwb_fixed:
3142 case ARM::VST1d32Qwb_fixed:
3143 case ARM::VST1d64Qwb_fixed:
3144 case ARM::VST2d8wb_fixed:
3145 case ARM::VST2d16wb_fixed:
3146 case ARM::VST2d32wb_fixed:
3147 case ARM::VST2q8wb_fixed:
3148 case ARM::VST2q16wb_fixed:
3149 case ARM::VST2q32wb_fixed:
3150 case ARM::VST2b8wb_fixed:
3151 case ARM::VST2b16wb_fixed:
3152 case ARM::VST2b32wb_fixed:
3153 break;
3154 }
3155
3156 // First input register
3157 switch (Inst.getOpcode()) {
3158 case ARM::VST1q16:
3159 case ARM::VST1q32:
3160 case ARM::VST1q64:
3161 case ARM::VST1q8:
3162 case ARM::VST1q16wb_fixed:
3163 case ARM::VST1q16wb_register:
3164 case ARM::VST1q32wb_fixed:
3165 case ARM::VST1q32wb_register:
3166 case ARM::VST1q64wb_fixed:
3167 case ARM::VST1q64wb_register:
3168 case ARM::VST1q8wb_fixed:
3169 case ARM::VST1q8wb_register:
3170 case ARM::VST2d16:
3171 case ARM::VST2d32:
3172 case ARM::VST2d8:
3173 case ARM::VST2d16wb_fixed:
3174 case ARM::VST2d16wb_register:
3175 case ARM::VST2d32wb_fixed:
3176 case ARM::VST2d32wb_register:
3177 case ARM::VST2d8wb_fixed:
3178 case ARM::VST2d8wb_register:
3179 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3180 return MCDisassembler::Fail;
3181 break;
3182 case ARM::VST2b16:
3183 case ARM::VST2b32:
3184 case ARM::VST2b8:
3185 case ARM::VST2b16wb_fixed:
3186 case ARM::VST2b16wb_register:
3187 case ARM::VST2b32wb_fixed:
3188 case ARM::VST2b32wb_register:
3189 case ARM::VST2b8wb_fixed:
3190 case ARM::VST2b8wb_register:
3191 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3192 return MCDisassembler::Fail;
3193 break;
3194 default:
3195 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3196 return MCDisassembler::Fail;
3197 }
3198
3199 // Second input register
3200 switch (Inst.getOpcode()) {
3201 case ARM::VST3d8:
3202 case ARM::VST3d16:
3203 case ARM::VST3d32:
3204 case ARM::VST3d8_UPD:
3205 case ARM::VST3d16_UPD:
3206 case ARM::VST3d32_UPD:
3207 case ARM::VST4d8:
3208 case ARM::VST4d16:
3209 case ARM::VST4d32:
3210 case ARM::VST4d8_UPD:
3211 case ARM::VST4d16_UPD:
3212 case ARM::VST4d32_UPD:
3213 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3214 return MCDisassembler::Fail;
3215 break;
3216 case ARM::VST3q8:
3217 case ARM::VST3q16:
3218 case ARM::VST3q32:
3219 case ARM::VST3q8_UPD:
3220 case ARM::VST3q16_UPD:
3221 case ARM::VST3q32_UPD:
3222 case ARM::VST4q8:
3223 case ARM::VST4q16:
3224 case ARM::VST4q32:
3225 case ARM::VST4q8_UPD:
3226 case ARM::VST4q16_UPD:
3227 case ARM::VST4q32_UPD:
3228 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3229 return MCDisassembler::Fail;
3230 break;
3231 default:
3232 break;
3233 }
3234
3235 // Third input register
3236 switch (Inst.getOpcode()) {
3237 case ARM::VST3d8:
3238 case ARM::VST3d16:
3239 case ARM::VST3d32:
3240 case ARM::VST3d8_UPD:
3241 case ARM::VST3d16_UPD:
3242 case ARM::VST3d32_UPD:
3243 case ARM::VST4d8:
3244 case ARM::VST4d16:
3245 case ARM::VST4d32:
3246 case ARM::VST4d8_UPD:
3247 case ARM::VST4d16_UPD:
3248 case ARM::VST4d32_UPD:
3249 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3250 return MCDisassembler::Fail;
3251 break;
3252 case ARM::VST3q8:
3253 case ARM::VST3q16:
3254 case ARM::VST3q32:
3255 case ARM::VST3q8_UPD:
3256 case ARM::VST3q16_UPD:
3257 case ARM::VST3q32_UPD:
3258 case ARM::VST4q8:
3259 case ARM::VST4q16:
3260 case ARM::VST4q32:
3261 case ARM::VST4q8_UPD:
3262 case ARM::VST4q16_UPD:
3263 case ARM::VST4q32_UPD:
3264 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3265 return MCDisassembler::Fail;
3266 break;
3267 default:
3268 break;
3269 }
3270
3271 // Fourth input register
3272 switch (Inst.getOpcode()) {
3273 case ARM::VST4d8:
3274 case ARM::VST4d16:
3275 case ARM::VST4d32:
3276 case ARM::VST4d8_UPD:
3277 case ARM::VST4d16_UPD:
3278 case ARM::VST4d32_UPD:
3279 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3280 return MCDisassembler::Fail;
3281 break;
3282 case ARM::VST4q8:
3283 case ARM::VST4q16:
3284 case ARM::VST4q32:
3285 case ARM::VST4q8_UPD:
3286 case ARM::VST4q16_UPD:
3287 case ARM::VST4q32_UPD:
3288 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3289 return MCDisassembler::Fail;
3290 break;
3291 default:
3292 break;
3293 }
3294
3295 return S;
3296 }
3297
DecodeVLD1DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3298 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
3299 uint64_t Address, const void *Decoder) {
3300 DecodeStatus S = MCDisassembler::Success;
3301
3302 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3303 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3304 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3305 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3306 unsigned align = fieldFromInstruction(Insn, 4, 1);
3307 unsigned size = fieldFromInstruction(Insn, 6, 2);
3308
3309 if (size == 0 && align == 1)
3310 return MCDisassembler::Fail;
3311 align *= (1 << size);
3312
3313 switch (Inst.getOpcode()) {
3314 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3315 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3316 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3317 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3318 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3319 return MCDisassembler::Fail;
3320 break;
3321 default:
3322 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3323 return MCDisassembler::Fail;
3324 break;
3325 }
3326 if (Rm != 0xF) {
3327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3328 return MCDisassembler::Fail;
3329 }
3330
3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3332 return MCDisassembler::Fail;
3333 Inst.addOperand(MCOperand::createImm(align));
3334
3335 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3336 // variant encodes Rm == 0xf. Anything else is a register offset post-
3337 // increment and we need to add the register operand to the instruction.
3338 if (Rm != 0xD && Rm != 0xF &&
3339 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3340 return MCDisassembler::Fail;
3341
3342 return S;
3343 }
3344
DecodeVLD2DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3345 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
3346 uint64_t Address, const void *Decoder) {
3347 DecodeStatus S = MCDisassembler::Success;
3348
3349 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3350 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3351 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3352 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3353 unsigned align = fieldFromInstruction(Insn, 4, 1);
3354 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3355 align *= 2*size;
3356
3357 switch (Inst.getOpcode()) {
3358 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3359 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3360 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3361 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3362 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3363 return MCDisassembler::Fail;
3364 break;
3365 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3366 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3367 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3368 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3369 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3370 return MCDisassembler::Fail;
3371 break;
3372 default:
3373 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3374 return MCDisassembler::Fail;
3375 break;
3376 }
3377
3378 if (Rm != 0xF)
3379 Inst.addOperand(MCOperand::createImm(0));
3380
3381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3382 return MCDisassembler::Fail;
3383 Inst.addOperand(MCOperand::createImm(align));
3384
3385 if (Rm != 0xD && Rm != 0xF) {
3386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3387 return MCDisassembler::Fail;
3388 }
3389
3390 return S;
3391 }
3392
DecodeVLD3DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3393 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3394 uint64_t Address, const void *Decoder) {
3395 DecodeStatus S = MCDisassembler::Success;
3396
3397 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3398 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3399 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3400 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3401 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3402
3403 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3404 return MCDisassembler::Fail;
3405 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3406 return MCDisassembler::Fail;
3407 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3408 return MCDisassembler::Fail;
3409 if (Rm != 0xF) {
3410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3411 return MCDisassembler::Fail;
3412 }
3413
3414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3415 return MCDisassembler::Fail;
3416 Inst.addOperand(MCOperand::createImm(0));
3417
3418 if (Rm == 0xD)
3419 Inst.addOperand(MCOperand::createReg(0));
3420 else if (Rm != 0xF) {
3421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3422 return MCDisassembler::Fail;
3423 }
3424
3425 return S;
3426 }
3427
DecodeVLD4DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3428 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3429 uint64_t Address, const void *Decoder) {
3430 DecodeStatus S = MCDisassembler::Success;
3431
3432 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3433 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3434 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3435 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3436 unsigned size = fieldFromInstruction(Insn, 6, 2);
3437 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3438 unsigned align = fieldFromInstruction(Insn, 4, 1);
3439
3440 if (size == 0x3) {
3441 if (align == 0)
3442 return MCDisassembler::Fail;
3443 align = 16;
3444 } else {
3445 if (size == 2) {
3446 align *= 8;
3447 } else {
3448 size = 1 << size;
3449 align *= 4*size;
3450 }
3451 }
3452
3453 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3454 return MCDisassembler::Fail;
3455 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3456 return MCDisassembler::Fail;
3457 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3458 return MCDisassembler::Fail;
3459 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3460 return MCDisassembler::Fail;
3461 if (Rm != 0xF) {
3462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3463 return MCDisassembler::Fail;
3464 }
3465
3466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3467 return MCDisassembler::Fail;
3468 Inst.addOperand(MCOperand::createImm(align));
3469
3470 if (Rm == 0xD)
3471 Inst.addOperand(MCOperand::createReg(0));
3472 else if (Rm != 0xF) {
3473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3474 return MCDisassembler::Fail;
3475 }
3476
3477 return S;
3478 }
3479
3480 static DecodeStatus
DecodeVMOVModImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3481 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
3482 uint64_t Address, const void *Decoder) {
3483 DecodeStatus S = MCDisassembler::Success;
3484
3485 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3486 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3487 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3488 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3489 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3490 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3491 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3492 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3493
3494 if (Q) {
3495 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3496 return MCDisassembler::Fail;
3497 } else {
3498 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3499 return MCDisassembler::Fail;
3500 }
3501
3502 Inst.addOperand(MCOperand::createImm(imm));
3503
3504 switch (Inst.getOpcode()) {
3505 case ARM::VORRiv4i16:
3506 case ARM::VORRiv2i32:
3507 case ARM::VBICiv4i16:
3508 case ARM::VBICiv2i32:
3509 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3510 return MCDisassembler::Fail;
3511 break;
3512 case ARM::VORRiv8i16:
3513 case ARM::VORRiv4i32:
3514 case ARM::VBICiv8i16:
3515 case ARM::VBICiv4i32:
3516 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3517 return MCDisassembler::Fail;
3518 break;
3519 default:
3520 break;
3521 }
3522
3523 return S;
3524 }
3525
3526 static DecodeStatus
DecodeMVEModImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3527 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
3528 uint64_t Address, const void *Decoder) {
3529 DecodeStatus S = MCDisassembler::Success;
3530
3531 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3532 fieldFromInstruction(Insn, 13, 3));
3533 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3534 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3535 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3536 imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3537 imm |= cmode << 8;
3538 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3539
3540 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3541 return MCDisassembler::Fail;
3542
3543 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3544 return MCDisassembler::Fail;
3545
3546 Inst.addOperand(MCOperand::createImm(imm));
3547
3548 Inst.addOperand(MCOperand::createImm(ARMVCC::None));
3549 Inst.addOperand(MCOperand::createReg(0));
3550 Inst.addOperand(MCOperand::createImm(0));
3551
3552 return S;
3553 }
3554
DecodeMVEVADCInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3555 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3556 uint64_t Address, const void *Decoder) {
3557 DecodeStatus S = MCDisassembler::Success;
3558
3559 unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3560 Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3561 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3562 return MCDisassembler::Fail;
3563 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3564
3565 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3566 Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3567 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3568 return MCDisassembler::Fail;
3569 unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3570 Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3571 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3572 return MCDisassembler::Fail;
3573 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3574 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3575 Inst.addOperand(MCOperand::createImm(Qd));
3576
3577 return S;
3578 }
3579
DecodeVSHLMaxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3580 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3581 uint64_t Address, const void *Decoder) {
3582 DecodeStatus S = MCDisassembler::Success;
3583
3584 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3585 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3586 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3587 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3588 unsigned size = fieldFromInstruction(Insn, 18, 2);
3589
3590 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3591 return MCDisassembler::Fail;
3592 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3593 return MCDisassembler::Fail;
3594 Inst.addOperand(MCOperand::createImm(8 << size));
3595
3596 return S;
3597 }
3598
DecodeShiftRight8Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3599 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3600 uint64_t Address, const void *Decoder) {
3601 Inst.addOperand(MCOperand::createImm(8 - Val));
3602 return MCDisassembler::Success;
3603 }
3604
DecodeShiftRight16Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3605 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3606 uint64_t Address, const void *Decoder) {
3607 Inst.addOperand(MCOperand::createImm(16 - Val));
3608 return MCDisassembler::Success;
3609 }
3610
DecodeShiftRight32Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3611 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3612 uint64_t Address, const void *Decoder) {
3613 Inst.addOperand(MCOperand::createImm(32 - Val));
3614 return MCDisassembler::Success;
3615 }
3616
DecodeShiftRight64Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3617 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3618 uint64_t Address, const void *Decoder) {
3619 Inst.addOperand(MCOperand::createImm(64 - Val));
3620 return MCDisassembler::Success;
3621 }
3622
DecodeTBLInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3623 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3624 uint64_t Address, const void *Decoder) {
3625 DecodeStatus S = MCDisassembler::Success;
3626
3627 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3628 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3629 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3630 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3631 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3632 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3633 unsigned op = fieldFromInstruction(Insn, 6, 1);
3634
3635 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3636 return MCDisassembler::Fail;
3637 if (op) {
3638 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3639 return MCDisassembler::Fail; // Writeback
3640 }
3641
3642 switch (Inst.getOpcode()) {
3643 case ARM::VTBL2:
3644 case ARM::VTBX2:
3645 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3646 return MCDisassembler::Fail;
3647 break;
3648 default:
3649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3650 return MCDisassembler::Fail;
3651 }
3652
3653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3654 return MCDisassembler::Fail;
3655
3656 return S;
3657 }
3658
DecodeThumbAddSpecialReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3659 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3660 uint64_t Address, const void *Decoder) {
3661 DecodeStatus S = MCDisassembler::Success;
3662
3663 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3664 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3665
3666 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3667 return MCDisassembler::Fail;
3668
3669 switch(Inst.getOpcode()) {
3670 default:
3671 return MCDisassembler::Fail;
3672 case ARM::tADR:
3673 break; // tADR does not explicitly represent the PC as an operand.
3674 case ARM::tADDrSPi:
3675 Inst.addOperand(MCOperand::createReg(ARM::SP));
3676 break;
3677 }
3678
3679 Inst.addOperand(MCOperand::createImm(imm));
3680 return S;
3681 }
3682
DecodeThumbBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3683 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3684 uint64_t Address, const void *Decoder) {
3685 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3686 true, 2, Inst, Decoder))
3687 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3688 return MCDisassembler::Success;
3689 }
3690
DecodeT2BROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3691 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3692 uint64_t Address, const void *Decoder) {
3693 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3694 true, 4, Inst, Decoder))
3695 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3696 return MCDisassembler::Success;
3697 }
3698
DecodeThumbCmpBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3699 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3700 uint64_t Address, const void *Decoder) {
3701 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3702 true, 2, Inst, Decoder))
3703 Inst.addOperand(MCOperand::createImm(Val << 1));
3704 return MCDisassembler::Success;
3705 }
3706
DecodeThumbAddrModeRR(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3707 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3708 uint64_t Address, const void *Decoder) {
3709 DecodeStatus S = MCDisassembler::Success;
3710
3711 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3712 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3713
3714 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3715 return MCDisassembler::Fail;
3716 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3717 return MCDisassembler::Fail;
3718
3719 return S;
3720 }
3721
DecodeThumbAddrModeIS(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3722 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3723 uint64_t Address, const void *Decoder) {
3724 DecodeStatus S = MCDisassembler::Success;
3725
3726 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3727 unsigned imm = fieldFromInstruction(Val, 3, 5);
3728
3729 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3730 return MCDisassembler::Fail;
3731 Inst.addOperand(MCOperand::createImm(imm));
3732
3733 return S;
3734 }
3735
DecodeThumbAddrModePC(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3736 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3737 uint64_t Address, const void *Decoder) {
3738 unsigned imm = Val << 2;
3739
3740 Inst.addOperand(MCOperand::createImm(imm));
3741 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3742
3743 return MCDisassembler::Success;
3744 }
3745
DecodeThumbAddrModeSP(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3746 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3747 uint64_t Address, const void *Decoder) {
3748 Inst.addOperand(MCOperand::createReg(ARM::SP));
3749 Inst.addOperand(MCOperand::createImm(Val));
3750
3751 return MCDisassembler::Success;
3752 }
3753
DecodeT2AddrModeSOReg(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3754 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3755 uint64_t Address, const void *Decoder) {
3756 DecodeStatus S = MCDisassembler::Success;
3757
3758 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3759 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3760 unsigned imm = fieldFromInstruction(Val, 0, 2);
3761
3762 // Thumb stores cannot use PC as dest register.
3763 switch (Inst.getOpcode()) {
3764 case ARM::t2STRHs:
3765 case ARM::t2STRBs:
3766 case ARM::t2STRs:
3767 if (Rn == 15)
3768 return MCDisassembler::Fail;
3769 break;
3770 default:
3771 break;
3772 }
3773
3774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3775 return MCDisassembler::Fail;
3776 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3777 return MCDisassembler::Fail;
3778 Inst.addOperand(MCOperand::createImm(imm));
3779
3780 return S;
3781 }
3782
DecodeT2LoadShift(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3783 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3784 uint64_t Address, const void *Decoder) {
3785 DecodeStatus S = MCDisassembler::Success;
3786
3787 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3788 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3789
3790 const FeatureBitset &featureBits =
3791 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3792
3793 bool hasMP = featureBits[ARM::FeatureMP];
3794 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3795
3796 if (Rn == 15) {
3797 switch (Inst.getOpcode()) {
3798 case ARM::t2LDRBs:
3799 Inst.setOpcode(ARM::t2LDRBpci);
3800 break;
3801 case ARM::t2LDRHs:
3802 Inst.setOpcode(ARM::t2LDRHpci);
3803 break;
3804 case ARM::t2LDRSHs:
3805 Inst.setOpcode(ARM::t2LDRSHpci);
3806 break;
3807 case ARM::t2LDRSBs:
3808 Inst.setOpcode(ARM::t2LDRSBpci);
3809 break;
3810 case ARM::t2LDRs:
3811 Inst.setOpcode(ARM::t2LDRpci);
3812 break;
3813 case ARM::t2PLDs:
3814 Inst.setOpcode(ARM::t2PLDpci);
3815 break;
3816 case ARM::t2PLIs:
3817 Inst.setOpcode(ARM::t2PLIpci);
3818 break;
3819 default:
3820 return MCDisassembler::Fail;
3821 }
3822
3823 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3824 }
3825
3826 if (Rt == 15) {
3827 switch (Inst.getOpcode()) {
3828 case ARM::t2LDRSHs:
3829 return MCDisassembler::Fail;
3830 case ARM::t2LDRHs:
3831 Inst.setOpcode(ARM::t2PLDWs);
3832 break;
3833 case ARM::t2LDRSBs:
3834 Inst.setOpcode(ARM::t2PLIs);
3835 break;
3836 default:
3837 break;
3838 }
3839 }
3840
3841 switch (Inst.getOpcode()) {
3842 case ARM::t2PLDs:
3843 break;
3844 case ARM::t2PLIs:
3845 if (!hasV7Ops)
3846 return MCDisassembler::Fail;
3847 break;
3848 case ARM::t2PLDWs:
3849 if (!hasV7Ops || !hasMP)
3850 return MCDisassembler::Fail;
3851 break;
3852 default:
3853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3854 return MCDisassembler::Fail;
3855 }
3856
3857 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3858 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3859 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3860 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3861 return MCDisassembler::Fail;
3862
3863 return S;
3864 }
3865
DecodeT2LoadImm8(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3866 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3867 uint64_t Address, const void* Decoder) {
3868 DecodeStatus S = MCDisassembler::Success;
3869
3870 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3871 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3872 unsigned U = fieldFromInstruction(Insn, 9, 1);
3873 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3874 imm |= (U << 8);
3875 imm |= (Rn << 9);
3876 unsigned add = fieldFromInstruction(Insn, 9, 1);
3877
3878 const FeatureBitset &featureBits =
3879 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3880
3881 bool hasMP = featureBits[ARM::FeatureMP];
3882 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3883
3884 if (Rn == 15) {
3885 switch (Inst.getOpcode()) {
3886 case ARM::t2LDRi8:
3887 Inst.setOpcode(ARM::t2LDRpci);
3888 break;
3889 case ARM::t2LDRBi8:
3890 Inst.setOpcode(ARM::t2LDRBpci);
3891 break;
3892 case ARM::t2LDRSBi8:
3893 Inst.setOpcode(ARM::t2LDRSBpci);
3894 break;
3895 case ARM::t2LDRHi8:
3896 Inst.setOpcode(ARM::t2LDRHpci);
3897 break;
3898 case ARM::t2LDRSHi8:
3899 Inst.setOpcode(ARM::t2LDRSHpci);
3900 break;
3901 case ARM::t2PLDi8:
3902 Inst.setOpcode(ARM::t2PLDpci);
3903 break;
3904 case ARM::t2PLIi8:
3905 Inst.setOpcode(ARM::t2PLIpci);
3906 break;
3907 default:
3908 return MCDisassembler::Fail;
3909 }
3910 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3911 }
3912
3913 if (Rt == 15) {
3914 switch (Inst.getOpcode()) {
3915 case ARM::t2LDRSHi8:
3916 return MCDisassembler::Fail;
3917 case ARM::t2LDRHi8:
3918 if (!add)
3919 Inst.setOpcode(ARM::t2PLDWi8);
3920 break;
3921 case ARM::t2LDRSBi8:
3922 Inst.setOpcode(ARM::t2PLIi8);
3923 break;
3924 default:
3925 break;
3926 }
3927 }
3928
3929 switch (Inst.getOpcode()) {
3930 case ARM::t2PLDi8:
3931 break;
3932 case ARM::t2PLIi8:
3933 if (!hasV7Ops)
3934 return MCDisassembler::Fail;
3935 break;
3936 case ARM::t2PLDWi8:
3937 if (!hasV7Ops || !hasMP)
3938 return MCDisassembler::Fail;
3939 break;
3940 default:
3941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3942 return MCDisassembler::Fail;
3943 }
3944
3945 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3946 return MCDisassembler::Fail;
3947 return S;
3948 }
3949
DecodeT2LoadImm12(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3950 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3951 uint64_t Address, const void* Decoder) {
3952 DecodeStatus S = MCDisassembler::Success;
3953
3954 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3955 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3956 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3957 imm |= (Rn << 13);
3958
3959 const FeatureBitset &featureBits =
3960 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3961
3962 bool hasMP = featureBits[ARM::FeatureMP];
3963 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3964
3965 if (Rn == 15) {
3966 switch (Inst.getOpcode()) {
3967 case ARM::t2LDRi12:
3968 Inst.setOpcode(ARM::t2LDRpci);
3969 break;
3970 case ARM::t2LDRHi12:
3971 Inst.setOpcode(ARM::t2LDRHpci);
3972 break;
3973 case ARM::t2LDRSHi12:
3974 Inst.setOpcode(ARM::t2LDRSHpci);
3975 break;
3976 case ARM::t2LDRBi12:
3977 Inst.setOpcode(ARM::t2LDRBpci);
3978 break;
3979 case ARM::t2LDRSBi12:
3980 Inst.setOpcode(ARM::t2LDRSBpci);
3981 break;
3982 case ARM::t2PLDi12:
3983 Inst.setOpcode(ARM::t2PLDpci);
3984 break;
3985 case ARM::t2PLIi12:
3986 Inst.setOpcode(ARM::t2PLIpci);
3987 break;
3988 default:
3989 return MCDisassembler::Fail;
3990 }
3991 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3992 }
3993
3994 if (Rt == 15) {
3995 switch (Inst.getOpcode()) {
3996 case ARM::t2LDRSHi12:
3997 return MCDisassembler::Fail;
3998 case ARM::t2LDRHi12:
3999 Inst.setOpcode(ARM::t2PLDWi12);
4000 break;
4001 case ARM::t2LDRSBi12:
4002 Inst.setOpcode(ARM::t2PLIi12);
4003 break;
4004 default:
4005 break;
4006 }
4007 }
4008
4009 switch (Inst.getOpcode()) {
4010 case ARM::t2PLDi12:
4011 break;
4012 case ARM::t2PLIi12:
4013 if (!hasV7Ops)
4014 return MCDisassembler::Fail;
4015 break;
4016 case ARM::t2PLDWi12:
4017 if (!hasV7Ops || !hasMP)
4018 return MCDisassembler::Fail;
4019 break;
4020 default:
4021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4022 return MCDisassembler::Fail;
4023 }
4024
4025 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4026 return MCDisassembler::Fail;
4027 return S;
4028 }
4029
DecodeT2LoadT(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4030 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
4031 uint64_t Address, const void* Decoder) {
4032 DecodeStatus S = MCDisassembler::Success;
4033
4034 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4035 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4036 unsigned imm = fieldFromInstruction(Insn, 0, 8);
4037 imm |= (Rn << 9);
4038
4039 if (Rn == 15) {
4040 switch (Inst.getOpcode()) {
4041 case ARM::t2LDRT:
4042 Inst.setOpcode(ARM::t2LDRpci);
4043 break;
4044 case ARM::t2LDRBT:
4045 Inst.setOpcode(ARM::t2LDRBpci);
4046 break;
4047 case ARM::t2LDRHT:
4048 Inst.setOpcode(ARM::t2LDRHpci);
4049 break;
4050 case ARM::t2LDRSBT:
4051 Inst.setOpcode(ARM::t2LDRSBpci);
4052 break;
4053 case ARM::t2LDRSHT:
4054 Inst.setOpcode(ARM::t2LDRSHpci);
4055 break;
4056 default:
4057 return MCDisassembler::Fail;
4058 }
4059 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4060 }
4061
4062 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4063 return MCDisassembler::Fail;
4064 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4065 return MCDisassembler::Fail;
4066 return S;
4067 }
4068
DecodeT2LoadLabel(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4069 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
4070 uint64_t Address, const void* Decoder) {
4071 DecodeStatus S = MCDisassembler::Success;
4072
4073 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4074 unsigned U = fieldFromInstruction(Insn, 23, 1);
4075 int imm = fieldFromInstruction(Insn, 0, 12);
4076
4077 const FeatureBitset &featureBits =
4078 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4079
4080 bool hasV7Ops = featureBits[ARM::HasV7Ops];
4081
4082 if (Rt == 15) {
4083 switch (Inst.getOpcode()) {
4084 case ARM::t2LDRBpci:
4085 case ARM::t2LDRHpci:
4086 Inst.setOpcode(ARM::t2PLDpci);
4087 break;
4088 case ARM::t2LDRSBpci:
4089 Inst.setOpcode(ARM::t2PLIpci);
4090 break;
4091 case ARM::t2LDRSHpci:
4092 return MCDisassembler::Fail;
4093 default:
4094 break;
4095 }
4096 }
4097
4098 switch(Inst.getOpcode()) {
4099 case ARM::t2PLDpci:
4100 break;
4101 case ARM::t2PLIpci:
4102 if (!hasV7Ops)
4103 return MCDisassembler::Fail;
4104 break;
4105 default:
4106 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4107 return MCDisassembler::Fail;
4108 }
4109
4110 if (!U) {
4111 // Special case for #-0.
4112 if (imm == 0)
4113 imm = INT32_MIN;
4114 else
4115 imm = -imm;
4116 }
4117 Inst.addOperand(MCOperand::createImm(imm));
4118
4119 return S;
4120 }
4121
DecodeT2Imm8S4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4122 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
4123 uint64_t Address, const void *Decoder) {
4124 if (Val == 0)
4125 Inst.addOperand(MCOperand::createImm(INT32_MIN));
4126 else {
4127 int imm = Val & 0xFF;
4128
4129 if (!(Val & 0x100)) imm *= -1;
4130 Inst.addOperand(MCOperand::createImm(imm * 4));
4131 }
4132
4133 return MCDisassembler::Success;
4134 }
4135
DecodeT2Imm7S4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4136 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4137 const void *Decoder) {
4138 if (Val == 0)
4139 Inst.addOperand(MCOperand::createImm(INT32_MIN));
4140 else {
4141 int imm = Val & 0x7F;
4142
4143 if (!(Val & 0x80))
4144 imm *= -1;
4145 Inst.addOperand(MCOperand::createImm(imm * 4));
4146 }
4147
4148 return MCDisassembler::Success;
4149 }
4150
DecodeT2AddrModeImm8s4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4151 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4152 uint64_t Address, const void *Decoder) {
4153 DecodeStatus S = MCDisassembler::Success;
4154
4155 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4156 unsigned imm = fieldFromInstruction(Val, 0, 9);
4157
4158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4159 return MCDisassembler::Fail;
4160 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4161 return MCDisassembler::Fail;
4162
4163 return S;
4164 }
4165
DecodeT2AddrModeImm7s4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4166 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4167 uint64_t Address,
4168 const void *Decoder) {
4169 DecodeStatus S = MCDisassembler::Success;
4170
4171 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4172 unsigned imm = fieldFromInstruction(Val, 0, 8);
4173
4174 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4175 return MCDisassembler::Fail;
4176 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4177 return MCDisassembler::Fail;
4178
4179 return S;
4180 }
4181
DecodeT2AddrModeImm0_1020s4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4182 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
4183 uint64_t Address, const void *Decoder) {
4184 DecodeStatus S = MCDisassembler::Success;
4185
4186 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4187 unsigned imm = fieldFromInstruction(Val, 0, 8);
4188
4189 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4190 return MCDisassembler::Fail;
4191
4192 Inst.addOperand(MCOperand::createImm(imm));
4193
4194 return S;
4195 }
4196
DecodeT2Imm8(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4197 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
4198 uint64_t Address, const void *Decoder) {
4199 int imm = Val & 0xFF;
4200 if (Val == 0)
4201 imm = INT32_MIN;
4202 else if (!(Val & 0x100))
4203 imm *= -1;
4204 Inst.addOperand(MCOperand::createImm(imm));
4205
4206 return MCDisassembler::Success;
4207 }
4208
4209 template<int shift>
DecodeT2Imm7(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4210 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
4211 uint64_t Address, const void *Decoder) {
4212 int imm = Val & 0x7F;
4213 if (Val == 0)
4214 imm = INT32_MIN;
4215 else if (!(Val & 0x80))
4216 imm *= -1;
4217 if (imm != INT32_MIN)
4218 imm *= (1U << shift);
4219 Inst.addOperand(MCOperand::createImm(imm));
4220
4221 return MCDisassembler::Success;
4222 }
4223
DecodeT2AddrModeImm8(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4224 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4225 uint64_t Address, const void *Decoder) {
4226 DecodeStatus S = MCDisassembler::Success;
4227
4228 unsigned Rn = fieldFromInstruction(Val, 9, 4);
4229 unsigned imm = fieldFromInstruction(Val, 0, 9);
4230
4231 // Thumb stores cannot use PC as dest register.
4232 switch (Inst.getOpcode()) {
4233 case ARM::t2STRT:
4234 case ARM::t2STRBT:
4235 case ARM::t2STRHT:
4236 case ARM::t2STRi8:
4237 case ARM::t2STRHi8:
4238 case ARM::t2STRBi8:
4239 if (Rn == 15)
4240 return MCDisassembler::Fail;
4241 break;
4242 default:
4243 break;
4244 }
4245
4246 // Some instructions always use an additive offset.
4247 switch (Inst.getOpcode()) {
4248 case ARM::t2LDRT:
4249 case ARM::t2LDRBT:
4250 case ARM::t2LDRHT:
4251 case ARM::t2LDRSBT:
4252 case ARM::t2LDRSHT:
4253 case ARM::t2STRT:
4254 case ARM::t2STRBT:
4255 case ARM::t2STRHT:
4256 imm |= 0x100;
4257 break;
4258 default:
4259 break;
4260 }
4261
4262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4263 return MCDisassembler::Fail;
4264 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4265 return MCDisassembler::Fail;
4266
4267 return S;
4268 }
4269
4270 template<int shift>
DecodeTAddrModeImm7(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4271 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4272 uint64_t Address,
4273 const void *Decoder) {
4274 DecodeStatus S = MCDisassembler::Success;
4275
4276 unsigned Rn = fieldFromInstruction(Val, 8, 3);
4277 unsigned imm = fieldFromInstruction(Val, 0, 8);
4278
4279 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4280 return MCDisassembler::Fail;
4281 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4282 return MCDisassembler::Fail;
4283
4284 return S;
4285 }
4286
4287 template<int shift, int WriteBack>
DecodeT2AddrModeImm7(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4288 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4289 uint64_t Address,
4290 const void *Decoder) {
4291 DecodeStatus S = MCDisassembler::Success;
4292
4293 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4294 unsigned imm = fieldFromInstruction(Val, 0, 8);
4295 if (WriteBack) {
4296 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4297 return MCDisassembler::Fail;
4298 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4299 return MCDisassembler::Fail;
4300 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4301 return MCDisassembler::Fail;
4302
4303 return S;
4304 }
4305
DecodeT2LdStPre(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4306 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4307 uint64_t Address, const void *Decoder) {
4308 DecodeStatus S = MCDisassembler::Success;
4309
4310 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4311 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4312 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4313 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4314 addr |= Rn << 9;
4315 unsigned load = fieldFromInstruction(Insn, 20, 1);
4316
4317 if (Rn == 15) {
4318 switch (Inst.getOpcode()) {
4319 case ARM::t2LDR_PRE:
4320 case ARM::t2LDR_POST:
4321 Inst.setOpcode(ARM::t2LDRpci);
4322 break;
4323 case ARM::t2LDRB_PRE:
4324 case ARM::t2LDRB_POST:
4325 Inst.setOpcode(ARM::t2LDRBpci);
4326 break;
4327 case ARM::t2LDRH_PRE:
4328 case ARM::t2LDRH_POST:
4329 Inst.setOpcode(ARM::t2LDRHpci);
4330 break;
4331 case ARM::t2LDRSB_PRE:
4332 case ARM::t2LDRSB_POST:
4333 if (Rt == 15)
4334 Inst.setOpcode(ARM::t2PLIpci);
4335 else
4336 Inst.setOpcode(ARM::t2LDRSBpci);
4337 break;
4338 case ARM::t2LDRSH_PRE:
4339 case ARM::t2LDRSH_POST:
4340 Inst.setOpcode(ARM::t2LDRSHpci);
4341 break;
4342 default:
4343 return MCDisassembler::Fail;
4344 }
4345 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4346 }
4347
4348 if (!load) {
4349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4350 return MCDisassembler::Fail;
4351 }
4352
4353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4354 return MCDisassembler::Fail;
4355
4356 if (load) {
4357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4358 return MCDisassembler::Fail;
4359 }
4360
4361 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4362 return MCDisassembler::Fail;
4363
4364 return S;
4365 }
4366
DecodeT2AddrModeImm12(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4367 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4368 uint64_t Address, const void *Decoder) {
4369 DecodeStatus S = MCDisassembler::Success;
4370
4371 unsigned Rn = fieldFromInstruction(Val, 13, 4);
4372 unsigned imm = fieldFromInstruction(Val, 0, 12);
4373
4374 // Thumb stores cannot use PC as dest register.
4375 switch (Inst.getOpcode()) {
4376 case ARM::t2STRi12:
4377 case ARM::t2STRBi12:
4378 case ARM::t2STRHi12:
4379 if (Rn == 15)
4380 return MCDisassembler::Fail;
4381 break;
4382 default:
4383 break;
4384 }
4385
4386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4387 return MCDisassembler::Fail;
4388 Inst.addOperand(MCOperand::createImm(imm));
4389
4390 return S;
4391 }
4392
DecodeThumbAddSPImm(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)4393 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
4394 uint64_t Address, const void *Decoder) {
4395 unsigned imm = fieldFromInstruction(Insn, 0, 7);
4396
4397 Inst.addOperand(MCOperand::createReg(ARM::SP));
4398 Inst.addOperand(MCOperand::createReg(ARM::SP));
4399 Inst.addOperand(MCOperand::createImm(imm));
4400
4401 return MCDisassembler::Success;
4402 }
4403
DecodeThumbAddSPReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)4404 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
4405 uint64_t Address, const void *Decoder) {
4406 DecodeStatus S = MCDisassembler::Success;
4407
4408 if (Inst.getOpcode() == ARM::tADDrSP) {
4409 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4410 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4411
4412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4413 return MCDisassembler::Fail;
4414 Inst.addOperand(MCOperand::createReg(ARM::SP));
4415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4416 return MCDisassembler::Fail;
4417 } else if (Inst.getOpcode() == ARM::tADDspr) {
4418 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4419
4420 Inst.addOperand(MCOperand::createReg(ARM::SP));
4421 Inst.addOperand(MCOperand::createReg(ARM::SP));
4422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4423 return MCDisassembler::Fail;
4424 }
4425
4426 return S;
4427 }
4428
DecodeThumbCPS(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)4429 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
4430 uint64_t Address, const void *Decoder) {
4431 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4432 unsigned flags = fieldFromInstruction(Insn, 0, 3);
4433
4434 Inst.addOperand(MCOperand::createImm(imod));
4435 Inst.addOperand(MCOperand::createImm(flags));
4436
4437 return MCDisassembler::Success;
4438 }
4439
DecodePostIdxReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4440 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4441 uint64_t Address, const void *Decoder) {
4442 DecodeStatus S = MCDisassembler::Success;
4443 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4444 unsigned add = fieldFromInstruction(Insn, 4, 1);
4445
4446 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4447 return MCDisassembler::Fail;
4448 Inst.addOperand(MCOperand::createImm(add));
4449
4450 return S;
4451 }
4452
DecodeMveAddrModeRQ(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4453 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
4454 uint64_t Address, const void *Decoder) {
4455 DecodeStatus S = MCDisassembler::Success;
4456 unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4457 unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4458
4459 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4460 return MCDisassembler::Fail;
4461 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4462 return MCDisassembler::Fail;
4463
4464 return S;
4465 }
4466
4467 template<int shift>
DecodeMveAddrModeQ(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4468 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
4469 uint64_t Address, const void *Decoder) {
4470 DecodeStatus S = MCDisassembler::Success;
4471 unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4472 int imm = fieldFromInstruction(Insn, 0, 7);
4473
4474 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4475 return MCDisassembler::Fail;
4476
4477 if(!fieldFromInstruction(Insn, 7, 1)) {
4478 if (imm == 0)
4479 imm = INT32_MIN; // indicate -0
4480 else
4481 imm *= -1;
4482 }
4483 if (imm != INT32_MIN)
4484 imm *= (1U << shift);
4485 Inst.addOperand(MCOperand::createImm(imm));
4486
4487 return S;
4488 }
4489
DecodeThumbBLXOffset(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4490 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
4491 uint64_t Address, const void *Decoder) {
4492 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
4493 // Note only one trailing zero not two. Also the J1 and J2 values are from
4494 // the encoded instruction. So here change to I1 and I2 values via:
4495 // I1 = NOT(J1 EOR S);
4496 // I2 = NOT(J2 EOR S);
4497 // and build the imm32 with two trailing zeros as documented:
4498 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
4499 unsigned S = (Val >> 23) & 1;
4500 unsigned J1 = (Val >> 22) & 1;
4501 unsigned J2 = (Val >> 21) & 1;
4502 unsigned I1 = !(J1 ^ S);
4503 unsigned I2 = !(J2 ^ S);
4504 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4505 int imm32 = SignExtend32<25>(tmp << 1);
4506
4507 if (!tryAddingSymbolicOperand(Address,
4508 (Address & ~2u) + imm32 + 4,
4509 true, 4, Inst, Decoder))
4510 Inst.addOperand(MCOperand::createImm(imm32));
4511 return MCDisassembler::Success;
4512 }
4513
DecodeCoprocessor(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4514 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
4515 uint64_t Address, const void *Decoder) {
4516 if (Val == 0xA || Val == 0xB)
4517 return MCDisassembler::Fail;
4518
4519 const FeatureBitset &featureBits =
4520 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4521
4522 if (!isValidCoprocessorNumber(Val, featureBits))
4523 return MCDisassembler::Fail;
4524
4525 Inst.addOperand(MCOperand::createImm(Val));
4526 return MCDisassembler::Success;
4527 }
4528
4529 static DecodeStatus
DecodeThumbTableBranch(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4530 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
4531 uint64_t Address, const void *Decoder) {
4532 const FeatureBitset &FeatureBits =
4533 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4534 DecodeStatus S = MCDisassembler::Success;
4535
4536 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4537 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4538
4539 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
4540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4541 return MCDisassembler::Fail;
4542 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4543 return MCDisassembler::Fail;
4544 return S;
4545 }
4546
4547 static DecodeStatus
DecodeThumb2BCCInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4548 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4549 uint64_t Address, const void *Decoder) {
4550 DecodeStatus S = MCDisassembler::Success;
4551
4552 unsigned pred = fieldFromInstruction(Insn, 22, 4);
4553 if (pred == 0xE || pred == 0xF) {
4554 unsigned opc = fieldFromInstruction(Insn, 4, 28);
4555 switch (opc) {
4556 default:
4557 return MCDisassembler::Fail;
4558 case 0xf3bf8f4:
4559 Inst.setOpcode(ARM::t2DSB);
4560 break;
4561 case 0xf3bf8f5:
4562 Inst.setOpcode(ARM::t2DMB);
4563 break;
4564 case 0xf3bf8f6:
4565 Inst.setOpcode(ARM::t2ISB);
4566 break;
4567 }
4568
4569 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4570 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4571 }
4572
4573 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4574 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4575 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4576 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4577 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4578
4579 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4580 return MCDisassembler::Fail;
4581 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4582 return MCDisassembler::Fail;
4583
4584 return S;
4585 }
4586
4587 // Decode a shifted immediate operand. These basically consist
4588 // of an 8-bit value, and a 4-bit directive that specifies either
4589 // a splat operation or a rotation.
DecodeT2SOImm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4590 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4591 uint64_t Address, const void *Decoder) {
4592 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4593 if (ctrl == 0) {
4594 unsigned byte = fieldFromInstruction(Val, 8, 2);
4595 unsigned imm = fieldFromInstruction(Val, 0, 8);
4596 switch (byte) {
4597 case 0:
4598 Inst.addOperand(MCOperand::createImm(imm));
4599 break;
4600 case 1:
4601 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4602 break;
4603 case 2:
4604 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4605 break;
4606 case 3:
4607 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4608 (imm << 8) | imm));
4609 break;
4610 }
4611 } else {
4612 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4613 unsigned rot = fieldFromInstruction(Val, 7, 5);
4614 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4615 Inst.addOperand(MCOperand::createImm(imm));
4616 }
4617
4618 return MCDisassembler::Success;
4619 }
4620
4621 static DecodeStatus
DecodeThumbBCCTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4622 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4623 uint64_t Address, const void *Decoder) {
4624 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4625 true, 2, Inst, Decoder))
4626 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4627 return MCDisassembler::Success;
4628 }
4629
DecodeThumbBLTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4630 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4631 uint64_t Address,
4632 const void *Decoder) {
4633 // Val is passed in as S:J1:J2:imm10:imm11
4634 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4635 // the encoded instruction. So here change to I1 and I2 values via:
4636 // I1 = NOT(J1 EOR S);
4637 // I2 = NOT(J2 EOR S);
4638 // and build the imm32 with one trailing zero as documented:
4639 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4640 unsigned S = (Val >> 23) & 1;
4641 unsigned J1 = (Val >> 22) & 1;
4642 unsigned J2 = (Val >> 21) & 1;
4643 unsigned I1 = !(J1 ^ S);
4644 unsigned I2 = !(J2 ^ S);
4645 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4646 int imm32 = SignExtend32<25>(tmp << 1);
4647
4648 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4649 true, 4, Inst, Decoder))
4650 Inst.addOperand(MCOperand::createImm(imm32));
4651 return MCDisassembler::Success;
4652 }
4653
DecodeMemBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4654 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4655 uint64_t Address, const void *Decoder) {
4656 if (Val & ~0xf)
4657 return MCDisassembler::Fail;
4658
4659 Inst.addOperand(MCOperand::createImm(Val));
4660 return MCDisassembler::Success;
4661 }
4662
DecodeInstSyncBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4663 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4664 uint64_t Address, const void *Decoder) {
4665 if (Val & ~0xf)
4666 return MCDisassembler::Fail;
4667
4668 Inst.addOperand(MCOperand::createImm(Val));
4669 return MCDisassembler::Success;
4670 }
4671
DecodeMSRMask(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4672 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4673 uint64_t Address, const void *Decoder) {
4674 DecodeStatus S = MCDisassembler::Success;
4675 const FeatureBitset &FeatureBits =
4676 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4677
4678 if (FeatureBits[ARM::FeatureMClass]) {
4679 unsigned ValLow = Val & 0xff;
4680
4681 // Validate the SYSm value first.
4682 switch (ValLow) {
4683 case 0: // apsr
4684 case 1: // iapsr
4685 case 2: // eapsr
4686 case 3: // xpsr
4687 case 5: // ipsr
4688 case 6: // epsr
4689 case 7: // iepsr
4690 case 8: // msp
4691 case 9: // psp
4692 case 16: // primask
4693 case 20: // control
4694 break;
4695 case 17: // basepri
4696 case 18: // basepri_max
4697 case 19: // faultmask
4698 if (!(FeatureBits[ARM::HasV7Ops]))
4699 // Values basepri, basepri_max and faultmask are only valid for v7m.
4700 return MCDisassembler::Fail;
4701 break;
4702 case 0x8a: // msplim_ns
4703 case 0x8b: // psplim_ns
4704 case 0x91: // basepri_ns
4705 case 0x93: // faultmask_ns
4706 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4707 return MCDisassembler::Fail;
4708 LLVM_FALLTHROUGH;
4709 case 10: // msplim
4710 case 11: // psplim
4711 case 0x88: // msp_ns
4712 case 0x89: // psp_ns
4713 case 0x90: // primask_ns
4714 case 0x94: // control_ns
4715 case 0x98: // sp_ns
4716 if (!(FeatureBits[ARM::Feature8MSecExt]))
4717 return MCDisassembler::Fail;
4718 break;
4719 default:
4720 // Architecturally defined as unpredictable
4721 S = MCDisassembler::SoftFail;
4722 break;
4723 }
4724
4725 if (Inst.getOpcode() == ARM::t2MSR_M) {
4726 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4727 if (!(FeatureBits[ARM::HasV7Ops])) {
4728 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4729 // unpredictable.
4730 if (Mask != 2)
4731 S = MCDisassembler::SoftFail;
4732 }
4733 else {
4734 // The ARMv7-M architecture stores an additional 2-bit mask value in
4735 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4736 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4737 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4738 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4739 // only if the processor includes the DSP extension.
4740 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4741 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4742 S = MCDisassembler::SoftFail;
4743 }
4744 }
4745 } else {
4746 // A/R class
4747 if (Val == 0)
4748 return MCDisassembler::Fail;
4749 }
4750 Inst.addOperand(MCOperand::createImm(Val));
4751 return S;
4752 }
4753
DecodeBankedReg(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4754 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4755 uint64_t Address, const void *Decoder) {
4756 unsigned R = fieldFromInstruction(Val, 5, 1);
4757 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4758
4759 // The table of encodings for these banked registers comes from B9.2.3 of the
4760 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4761 // neater. So by fiat, these values are UNPREDICTABLE:
4762 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4763 return MCDisassembler::Fail;
4764
4765 Inst.addOperand(MCOperand::createImm(Val));
4766 return MCDisassembler::Success;
4767 }
4768
DecodeDoubleRegLoad(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4769 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4770 uint64_t Address, const void *Decoder) {
4771 DecodeStatus S = MCDisassembler::Success;
4772
4773 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4774 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4775 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4776
4777 if (Rn == 0xF)
4778 S = MCDisassembler::SoftFail;
4779
4780 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4781 return MCDisassembler::Fail;
4782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4783 return MCDisassembler::Fail;
4784 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4785 return MCDisassembler::Fail;
4786
4787 return S;
4788 }
4789
DecodeDoubleRegStore(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4790 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4791 uint64_t Address,
4792 const void *Decoder) {
4793 DecodeStatus S = MCDisassembler::Success;
4794
4795 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4796 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4797 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4798 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4799
4800 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4801 return MCDisassembler::Fail;
4802
4803 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4804 S = MCDisassembler::SoftFail;
4805
4806 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4807 return MCDisassembler::Fail;
4808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4809 return MCDisassembler::Fail;
4810 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4811 return MCDisassembler::Fail;
4812
4813 return S;
4814 }
4815
DecodeLDRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4816 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4817 uint64_t Address, const void *Decoder) {
4818 DecodeStatus S = MCDisassembler::Success;
4819
4820 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4821 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4822 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4823 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4824 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4825 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4826
4827 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4828
4829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4830 return MCDisassembler::Fail;
4831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4832 return MCDisassembler::Fail;
4833 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4834 return MCDisassembler::Fail;
4835 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4836 return MCDisassembler::Fail;
4837
4838 return S;
4839 }
4840
DecodeLDRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4841 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4842 uint64_t Address, const void *Decoder) {
4843 DecodeStatus S = MCDisassembler::Success;
4844
4845 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4846 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4847 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4848 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4849 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4850 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4851 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4852
4853 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4854 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4855
4856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4857 return MCDisassembler::Fail;
4858 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4859 return MCDisassembler::Fail;
4860 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4861 return MCDisassembler::Fail;
4862 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4863 return MCDisassembler::Fail;
4864
4865 return S;
4866 }
4867
DecodeSTRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4868 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4869 uint64_t Address, const void *Decoder) {
4870 DecodeStatus S = MCDisassembler::Success;
4871
4872 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4873 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4874 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4875 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4876 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4877 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4878
4879 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4880
4881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4882 return MCDisassembler::Fail;
4883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4884 return MCDisassembler::Fail;
4885 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4886 return MCDisassembler::Fail;
4887 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4888 return MCDisassembler::Fail;
4889
4890 return S;
4891 }
4892
DecodeSTRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4893 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4894 uint64_t Address, const void *Decoder) {
4895 DecodeStatus S = MCDisassembler::Success;
4896
4897 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4898 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4899 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4900 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4901 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4902 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4903
4904 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4905
4906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4907 return MCDisassembler::Fail;
4908 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4909 return MCDisassembler::Fail;
4910 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4911 return MCDisassembler::Fail;
4912 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4913 return MCDisassembler::Fail;
4914
4915 return S;
4916 }
4917
DecodeVLD1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4918 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4919 uint64_t Address, const void *Decoder) {
4920 DecodeStatus S = MCDisassembler::Success;
4921
4922 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4923 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4924 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4925 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4926 unsigned size = fieldFromInstruction(Insn, 10, 2);
4927
4928 unsigned align = 0;
4929 unsigned index = 0;
4930 switch (size) {
4931 default:
4932 return MCDisassembler::Fail;
4933 case 0:
4934 if (fieldFromInstruction(Insn, 4, 1))
4935 return MCDisassembler::Fail; // UNDEFINED
4936 index = fieldFromInstruction(Insn, 5, 3);
4937 break;
4938 case 1:
4939 if (fieldFromInstruction(Insn, 5, 1))
4940 return MCDisassembler::Fail; // UNDEFINED
4941 index = fieldFromInstruction(Insn, 6, 2);
4942 if (fieldFromInstruction(Insn, 4, 1))
4943 align = 2;
4944 break;
4945 case 2:
4946 if (fieldFromInstruction(Insn, 6, 1))
4947 return MCDisassembler::Fail; // UNDEFINED
4948 index = fieldFromInstruction(Insn, 7, 1);
4949
4950 switch (fieldFromInstruction(Insn, 4, 2)) {
4951 case 0 :
4952 align = 0; break;
4953 case 3:
4954 align = 4; break;
4955 default:
4956 return MCDisassembler::Fail;
4957 }
4958 break;
4959 }
4960
4961 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4962 return MCDisassembler::Fail;
4963 if (Rm != 0xF) { // Writeback
4964 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4965 return MCDisassembler::Fail;
4966 }
4967 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4968 return MCDisassembler::Fail;
4969 Inst.addOperand(MCOperand::createImm(align));
4970 if (Rm != 0xF) {
4971 if (Rm != 0xD) {
4972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4973 return MCDisassembler::Fail;
4974 } else
4975 Inst.addOperand(MCOperand::createReg(0));
4976 }
4977
4978 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4979 return MCDisassembler::Fail;
4980 Inst.addOperand(MCOperand::createImm(index));
4981
4982 return S;
4983 }
4984
DecodeVST1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4985 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4986 uint64_t Address, const void *Decoder) {
4987 DecodeStatus S = MCDisassembler::Success;
4988
4989 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4990 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4991 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4992 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4993 unsigned size = fieldFromInstruction(Insn, 10, 2);
4994
4995 unsigned align = 0;
4996 unsigned index = 0;
4997 switch (size) {
4998 default:
4999 return MCDisassembler::Fail;
5000 case 0:
5001 if (fieldFromInstruction(Insn, 4, 1))
5002 return MCDisassembler::Fail; // UNDEFINED
5003 index = fieldFromInstruction(Insn, 5, 3);
5004 break;
5005 case 1:
5006 if (fieldFromInstruction(Insn, 5, 1))
5007 return MCDisassembler::Fail; // UNDEFINED
5008 index = fieldFromInstruction(Insn, 6, 2);
5009 if (fieldFromInstruction(Insn, 4, 1))
5010 align = 2;
5011 break;
5012 case 2:
5013 if (fieldFromInstruction(Insn, 6, 1))
5014 return MCDisassembler::Fail; // UNDEFINED
5015 index = fieldFromInstruction(Insn, 7, 1);
5016
5017 switch (fieldFromInstruction(Insn, 4, 2)) {
5018 case 0:
5019 align = 0; break;
5020 case 3:
5021 align = 4; break;
5022 default:
5023 return MCDisassembler::Fail;
5024 }
5025 break;
5026 }
5027
5028 if (Rm != 0xF) { // Writeback
5029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5030 return MCDisassembler::Fail;
5031 }
5032 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5033 return MCDisassembler::Fail;
5034 Inst.addOperand(MCOperand::createImm(align));
5035 if (Rm != 0xF) {
5036 if (Rm != 0xD) {
5037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5038 return MCDisassembler::Fail;
5039 } else
5040 Inst.addOperand(MCOperand::createReg(0));
5041 }
5042
5043 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5044 return MCDisassembler::Fail;
5045 Inst.addOperand(MCOperand::createImm(index));
5046
5047 return S;
5048 }
5049
DecodeVLD2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5050 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
5051 uint64_t Address, const void *Decoder) {
5052 DecodeStatus S = MCDisassembler::Success;
5053
5054 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5055 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5056 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5057 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5058 unsigned size = fieldFromInstruction(Insn, 10, 2);
5059
5060 unsigned align = 0;
5061 unsigned index = 0;
5062 unsigned inc = 1;
5063 switch (size) {
5064 default:
5065 return MCDisassembler::Fail;
5066 case 0:
5067 index = fieldFromInstruction(Insn, 5, 3);
5068 if (fieldFromInstruction(Insn, 4, 1))
5069 align = 2;
5070 break;
5071 case 1:
5072 index = fieldFromInstruction(Insn, 6, 2);
5073 if (fieldFromInstruction(Insn, 4, 1))
5074 align = 4;
5075 if (fieldFromInstruction(Insn, 5, 1))
5076 inc = 2;
5077 break;
5078 case 2:
5079 if (fieldFromInstruction(Insn, 5, 1))
5080 return MCDisassembler::Fail; // UNDEFINED
5081 index = fieldFromInstruction(Insn, 7, 1);
5082 if (fieldFromInstruction(Insn, 4, 1) != 0)
5083 align = 8;
5084 if (fieldFromInstruction(Insn, 6, 1))
5085 inc = 2;
5086 break;
5087 }
5088
5089 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5090 return MCDisassembler::Fail;
5091 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5092 return MCDisassembler::Fail;
5093 if (Rm != 0xF) { // Writeback
5094 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5095 return MCDisassembler::Fail;
5096 }
5097 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5098 return MCDisassembler::Fail;
5099 Inst.addOperand(MCOperand::createImm(align));
5100 if (Rm != 0xF) {
5101 if (Rm != 0xD) {
5102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5103 return MCDisassembler::Fail;
5104 } else
5105 Inst.addOperand(MCOperand::createReg(0));
5106 }
5107
5108 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5109 return MCDisassembler::Fail;
5110 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5111 return MCDisassembler::Fail;
5112 Inst.addOperand(MCOperand::createImm(index));
5113
5114 return S;
5115 }
5116
DecodeVST2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5117 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
5118 uint64_t Address, const void *Decoder) {
5119 DecodeStatus S = MCDisassembler::Success;
5120
5121 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5122 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5123 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5124 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5125 unsigned size = fieldFromInstruction(Insn, 10, 2);
5126
5127 unsigned align = 0;
5128 unsigned index = 0;
5129 unsigned inc = 1;
5130 switch (size) {
5131 default:
5132 return MCDisassembler::Fail;
5133 case 0:
5134 index = fieldFromInstruction(Insn, 5, 3);
5135 if (fieldFromInstruction(Insn, 4, 1))
5136 align = 2;
5137 break;
5138 case 1:
5139 index = fieldFromInstruction(Insn, 6, 2);
5140 if (fieldFromInstruction(Insn, 4, 1))
5141 align = 4;
5142 if (fieldFromInstruction(Insn, 5, 1))
5143 inc = 2;
5144 break;
5145 case 2:
5146 if (fieldFromInstruction(Insn, 5, 1))
5147 return MCDisassembler::Fail; // UNDEFINED
5148 index = fieldFromInstruction(Insn, 7, 1);
5149 if (fieldFromInstruction(Insn, 4, 1) != 0)
5150 align = 8;
5151 if (fieldFromInstruction(Insn, 6, 1))
5152 inc = 2;
5153 break;
5154 }
5155
5156 if (Rm != 0xF) { // Writeback
5157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5158 return MCDisassembler::Fail;
5159 }
5160 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5161 return MCDisassembler::Fail;
5162 Inst.addOperand(MCOperand::createImm(align));
5163 if (Rm != 0xF) {
5164 if (Rm != 0xD) {
5165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5166 return MCDisassembler::Fail;
5167 } else
5168 Inst.addOperand(MCOperand::createReg(0));
5169 }
5170
5171 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5172 return MCDisassembler::Fail;
5173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5174 return MCDisassembler::Fail;
5175 Inst.addOperand(MCOperand::createImm(index));
5176
5177 return S;
5178 }
5179
DecodeVLD3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5180 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
5181 uint64_t Address, const void *Decoder) {
5182 DecodeStatus S = MCDisassembler::Success;
5183
5184 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5185 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5186 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5187 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5188 unsigned size = fieldFromInstruction(Insn, 10, 2);
5189
5190 unsigned align = 0;
5191 unsigned index = 0;
5192 unsigned inc = 1;
5193 switch (size) {
5194 default:
5195 return MCDisassembler::Fail;
5196 case 0:
5197 if (fieldFromInstruction(Insn, 4, 1))
5198 return MCDisassembler::Fail; // UNDEFINED
5199 index = fieldFromInstruction(Insn, 5, 3);
5200 break;
5201 case 1:
5202 if (fieldFromInstruction(Insn, 4, 1))
5203 return MCDisassembler::Fail; // UNDEFINED
5204 index = fieldFromInstruction(Insn, 6, 2);
5205 if (fieldFromInstruction(Insn, 5, 1))
5206 inc = 2;
5207 break;
5208 case 2:
5209 if (fieldFromInstruction(Insn, 4, 2))
5210 return MCDisassembler::Fail; // UNDEFINED
5211 index = fieldFromInstruction(Insn, 7, 1);
5212 if (fieldFromInstruction(Insn, 6, 1))
5213 inc = 2;
5214 break;
5215 }
5216
5217 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5218 return MCDisassembler::Fail;
5219 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5220 return MCDisassembler::Fail;
5221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5222 return MCDisassembler::Fail;
5223
5224 if (Rm != 0xF) { // Writeback
5225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5226 return MCDisassembler::Fail;
5227 }
5228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5229 return MCDisassembler::Fail;
5230 Inst.addOperand(MCOperand::createImm(align));
5231 if (Rm != 0xF) {
5232 if (Rm != 0xD) {
5233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5234 return MCDisassembler::Fail;
5235 } else
5236 Inst.addOperand(MCOperand::createReg(0));
5237 }
5238
5239 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5240 return MCDisassembler::Fail;
5241 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5242 return MCDisassembler::Fail;
5243 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5244 return MCDisassembler::Fail;
5245 Inst.addOperand(MCOperand::createImm(index));
5246
5247 return S;
5248 }
5249
DecodeVST3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5250 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
5251 uint64_t Address, const void *Decoder) {
5252 DecodeStatus S = MCDisassembler::Success;
5253
5254 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5255 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5256 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5257 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5258 unsigned size = fieldFromInstruction(Insn, 10, 2);
5259
5260 unsigned align = 0;
5261 unsigned index = 0;
5262 unsigned inc = 1;
5263 switch (size) {
5264 default:
5265 return MCDisassembler::Fail;
5266 case 0:
5267 if (fieldFromInstruction(Insn, 4, 1))
5268 return MCDisassembler::Fail; // UNDEFINED
5269 index = fieldFromInstruction(Insn, 5, 3);
5270 break;
5271 case 1:
5272 if (fieldFromInstruction(Insn, 4, 1))
5273 return MCDisassembler::Fail; // UNDEFINED
5274 index = fieldFromInstruction(Insn, 6, 2);
5275 if (fieldFromInstruction(Insn, 5, 1))
5276 inc = 2;
5277 break;
5278 case 2:
5279 if (fieldFromInstruction(Insn, 4, 2))
5280 return MCDisassembler::Fail; // UNDEFINED
5281 index = fieldFromInstruction(Insn, 7, 1);
5282 if (fieldFromInstruction(Insn, 6, 1))
5283 inc = 2;
5284 break;
5285 }
5286
5287 if (Rm != 0xF) { // Writeback
5288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5289 return MCDisassembler::Fail;
5290 }
5291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5292 return MCDisassembler::Fail;
5293 Inst.addOperand(MCOperand::createImm(align));
5294 if (Rm != 0xF) {
5295 if (Rm != 0xD) {
5296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5297 return MCDisassembler::Fail;
5298 } else
5299 Inst.addOperand(MCOperand::createReg(0));
5300 }
5301
5302 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5303 return MCDisassembler::Fail;
5304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5305 return MCDisassembler::Fail;
5306 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5307 return MCDisassembler::Fail;
5308 Inst.addOperand(MCOperand::createImm(index));
5309
5310 return S;
5311 }
5312
DecodeVLD4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5313 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
5314 uint64_t Address, const void *Decoder) {
5315 DecodeStatus S = MCDisassembler::Success;
5316
5317 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5318 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5319 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5320 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5321 unsigned size = fieldFromInstruction(Insn, 10, 2);
5322
5323 unsigned align = 0;
5324 unsigned index = 0;
5325 unsigned inc = 1;
5326 switch (size) {
5327 default:
5328 return MCDisassembler::Fail;
5329 case 0:
5330 if (fieldFromInstruction(Insn, 4, 1))
5331 align = 4;
5332 index = fieldFromInstruction(Insn, 5, 3);
5333 break;
5334 case 1:
5335 if (fieldFromInstruction(Insn, 4, 1))
5336 align = 8;
5337 index = fieldFromInstruction(Insn, 6, 2);
5338 if (fieldFromInstruction(Insn, 5, 1))
5339 inc = 2;
5340 break;
5341 case 2:
5342 switch (fieldFromInstruction(Insn, 4, 2)) {
5343 case 0:
5344 align = 0; break;
5345 case 3:
5346 return MCDisassembler::Fail;
5347 default:
5348 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
5349 }
5350
5351 index = fieldFromInstruction(Insn, 7, 1);
5352 if (fieldFromInstruction(Insn, 6, 1))
5353 inc = 2;
5354 break;
5355 }
5356
5357 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5358 return MCDisassembler::Fail;
5359 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5360 return MCDisassembler::Fail;
5361 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5362 return MCDisassembler::Fail;
5363 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5364 return MCDisassembler::Fail;
5365
5366 if (Rm != 0xF) { // Writeback
5367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5368 return MCDisassembler::Fail;
5369 }
5370 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5371 return MCDisassembler::Fail;
5372 Inst.addOperand(MCOperand::createImm(align));
5373 if (Rm != 0xF) {
5374 if (Rm != 0xD) {
5375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5376 return MCDisassembler::Fail;
5377 } else
5378 Inst.addOperand(MCOperand::createReg(0));
5379 }
5380
5381 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5382 return MCDisassembler::Fail;
5383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5384 return MCDisassembler::Fail;
5385 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5386 return MCDisassembler::Fail;
5387 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5388 return MCDisassembler::Fail;
5389 Inst.addOperand(MCOperand::createImm(index));
5390
5391 return S;
5392 }
5393
DecodeVST4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5394 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
5395 uint64_t Address, const void *Decoder) {
5396 DecodeStatus S = MCDisassembler::Success;
5397
5398 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5399 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5400 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5401 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5402 unsigned size = fieldFromInstruction(Insn, 10, 2);
5403
5404 unsigned align = 0;
5405 unsigned index = 0;
5406 unsigned inc = 1;
5407 switch (size) {
5408 default:
5409 return MCDisassembler::Fail;
5410 case 0:
5411 if (fieldFromInstruction(Insn, 4, 1))
5412 align = 4;
5413 index = fieldFromInstruction(Insn, 5, 3);
5414 break;
5415 case 1:
5416 if (fieldFromInstruction(Insn, 4, 1))
5417 align = 8;
5418 index = fieldFromInstruction(Insn, 6, 2);
5419 if (fieldFromInstruction(Insn, 5, 1))
5420 inc = 2;
5421 break;
5422 case 2:
5423 switch (fieldFromInstruction(Insn, 4, 2)) {
5424 case 0:
5425 align = 0; break;
5426 case 3:
5427 return MCDisassembler::Fail;
5428 default:
5429 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
5430 }
5431
5432 index = fieldFromInstruction(Insn, 7, 1);
5433 if (fieldFromInstruction(Insn, 6, 1))
5434 inc = 2;
5435 break;
5436 }
5437
5438 if (Rm != 0xF) { // Writeback
5439 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5440 return MCDisassembler::Fail;
5441 }
5442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5443 return MCDisassembler::Fail;
5444 Inst.addOperand(MCOperand::createImm(align));
5445 if (Rm != 0xF) {
5446 if (Rm != 0xD) {
5447 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5448 return MCDisassembler::Fail;
5449 } else
5450 Inst.addOperand(MCOperand::createReg(0));
5451 }
5452
5453 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5454 return MCDisassembler::Fail;
5455 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5456 return MCDisassembler::Fail;
5457 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5458 return MCDisassembler::Fail;
5459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5460 return MCDisassembler::Fail;
5461 Inst.addOperand(MCOperand::createImm(index));
5462
5463 return S;
5464 }
5465
DecodeVMOVSRR(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5466 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
5467 uint64_t Address, const void *Decoder) {
5468 DecodeStatus S = MCDisassembler::Success;
5469 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5470 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5471 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
5472 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5473 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5474
5475 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5476 S = MCDisassembler::SoftFail;
5477
5478 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5479 return MCDisassembler::Fail;
5480 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5481 return MCDisassembler::Fail;
5482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
5483 return MCDisassembler::Fail;
5484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5485 return MCDisassembler::Fail;
5486 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5487 return MCDisassembler::Fail;
5488
5489 return S;
5490 }
5491
DecodeVMOVRRS(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5492 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
5493 uint64_t Address, const void *Decoder) {
5494 DecodeStatus S = MCDisassembler::Success;
5495 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5496 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5497 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
5498 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5499 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5500
5501 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5502 S = MCDisassembler::SoftFail;
5503
5504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
5505 return MCDisassembler::Fail;
5506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5507 return MCDisassembler::Fail;
5508 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5509 return MCDisassembler::Fail;
5510 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5511 return MCDisassembler::Fail;
5512 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5513 return MCDisassembler::Fail;
5514
5515 return S;
5516 }
5517
DecodeIT(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5518 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
5519 uint64_t Address, const void *Decoder) {
5520 DecodeStatus S = MCDisassembler::Success;
5521 unsigned pred = fieldFromInstruction(Insn, 4, 4);
5522 unsigned mask = fieldFromInstruction(Insn, 0, 4);
5523
5524 if (pred == 0xF) {
5525 pred = 0xE;
5526 S = MCDisassembler::SoftFail;
5527 }
5528
5529 if (mask == 0x0)
5530 return MCDisassembler::Fail;
5531
5532 // IT masks are encoded as a sequence of replacement low-order bits
5533 // for the condition code. So if the low bit of the starting
5534 // condition code is 1, then we have to flip all the bits above the
5535 // terminating bit (which is the lowest 1 bit).
5536 if (pred & 1) {
5537 unsigned LowBit = mask & -mask;
5538 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
5539 mask ^= BitsAboveLowBit;
5540 }
5541
5542 Inst.addOperand(MCOperand::createImm(pred));
5543 Inst.addOperand(MCOperand::createImm(mask));
5544 return S;
5545 }
5546
5547 static DecodeStatus
DecodeT2LDRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5548 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
5549 uint64_t Address, const void *Decoder) {
5550 DecodeStatus S = MCDisassembler::Success;
5551
5552 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5553 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5554 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5555 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5556 unsigned W = fieldFromInstruction(Insn, 21, 1);
5557 unsigned U = fieldFromInstruction(Insn, 23, 1);
5558 unsigned P = fieldFromInstruction(Insn, 24, 1);
5559 bool writeback = (W == 1) | (P == 0);
5560
5561 addr |= (U << 8) | (Rn << 9);
5562
5563 if (writeback && (Rn == Rt || Rn == Rt2))
5564 Check(S, MCDisassembler::SoftFail);
5565 if (Rt == Rt2)
5566 Check(S, MCDisassembler::SoftFail);
5567
5568 // Rt
5569 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5570 return MCDisassembler::Fail;
5571 // Rt2
5572 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5573 return MCDisassembler::Fail;
5574 // Writeback operand
5575 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5576 return MCDisassembler::Fail;
5577 // addr
5578 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5579 return MCDisassembler::Fail;
5580
5581 return S;
5582 }
5583
5584 static DecodeStatus
DecodeT2STRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5585 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5586 uint64_t Address, const void *Decoder) {
5587 DecodeStatus S = MCDisassembler::Success;
5588
5589 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5590 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5591 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5592 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5593 unsigned W = fieldFromInstruction(Insn, 21, 1);
5594 unsigned U = fieldFromInstruction(Insn, 23, 1);
5595 unsigned P = fieldFromInstruction(Insn, 24, 1);
5596 bool writeback = (W == 1) | (P == 0);
5597
5598 addr |= (U << 8) | (Rn << 9);
5599
5600 if (writeback && (Rn == Rt || Rn == Rt2))
5601 Check(S, MCDisassembler::SoftFail);
5602
5603 // Writeback operand
5604 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5605 return MCDisassembler::Fail;
5606 // Rt
5607 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5608 return MCDisassembler::Fail;
5609 // Rt2
5610 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5611 return MCDisassembler::Fail;
5612 // addr
5613 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5614 return MCDisassembler::Fail;
5615
5616 return S;
5617 }
5618
DecodeT2Adr(MCInst & Inst,uint32_t Insn,uint64_t Address,const void * Decoder)5619 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5620 uint64_t Address, const void *Decoder) {
5621 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5622 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5623 if (sign1 != sign2) return MCDisassembler::Fail;
5624 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
5625 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
5626 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
5627
5628 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5629 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5630 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5631 // If sign, then it is decreasing the address.
5632 if (sign1) {
5633 // Following ARMv7 Architecture Manual, when the offset
5634 // is zero, it is decoded as a subw, not as a adr.w
5635 if (!Val) {
5636 Inst.setOpcode(ARM::t2SUBri12);
5637 Inst.addOperand(MCOperand::createReg(ARM::PC));
5638 } else
5639 Val = -Val;
5640 }
5641 Inst.addOperand(MCOperand::createImm(Val));
5642 return S;
5643 }
5644
DecodeT2ShifterImmOperand(MCInst & Inst,uint32_t Val,uint64_t Address,const void * Decoder)5645 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5646 uint64_t Address,
5647 const void *Decoder) {
5648 DecodeStatus S = MCDisassembler::Success;
5649
5650 // Shift of "asr #32" is not allowed in Thumb2 mode.
5651 if (Val == 0x20) S = MCDisassembler::Fail;
5652 Inst.addOperand(MCOperand::createImm(Val));
5653 return S;
5654 }
5655
DecodeSwap(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5656 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5657 uint64_t Address, const void *Decoder) {
5658 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5659 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5660 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5661 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5662
5663 if (pred == 0xF)
5664 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5665
5666 DecodeStatus S = MCDisassembler::Success;
5667
5668 if (Rt == Rn || Rn == Rt2)
5669 S = MCDisassembler::SoftFail;
5670
5671 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5672 return MCDisassembler::Fail;
5673 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5674 return MCDisassembler::Fail;
5675 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5676 return MCDisassembler::Fail;
5677 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5678 return MCDisassembler::Fail;
5679
5680 return S;
5681 }
5682
DecodeVCVTD(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5683 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5684 uint64_t Address, const void *Decoder) {
5685 const FeatureBitset &featureBits =
5686 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5687 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5688
5689 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5690 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5691 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5692 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5693 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5694 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5695 unsigned op = fieldFromInstruction(Insn, 5, 1);
5696
5697 DecodeStatus S = MCDisassembler::Success;
5698
5699 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5700 if (!(imm & 0x38)) {
5701 if (cmode == 0xF) {
5702 if (op == 1) return MCDisassembler::Fail;
5703 Inst.setOpcode(ARM::VMOVv2f32);
5704 }
5705 if (hasFullFP16) {
5706 if (cmode == 0xE) {
5707 if (op == 1) {
5708 Inst.setOpcode(ARM::VMOVv1i64);
5709 } else {
5710 Inst.setOpcode(ARM::VMOVv8i8);
5711 }
5712 }
5713 if (cmode == 0xD) {
5714 if (op == 1) {
5715 Inst.setOpcode(ARM::VMVNv2i32);
5716 } else {
5717 Inst.setOpcode(ARM::VMOVv2i32);
5718 }
5719 }
5720 if (cmode == 0xC) {
5721 if (op == 1) {
5722 Inst.setOpcode(ARM::VMVNv2i32);
5723 } else {
5724 Inst.setOpcode(ARM::VMOVv2i32);
5725 }
5726 }
5727 }
5728 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5729 }
5730
5731 if (!(imm & 0x20)) return MCDisassembler::Fail;
5732
5733 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5734 return MCDisassembler::Fail;
5735 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5736 return MCDisassembler::Fail;
5737 Inst.addOperand(MCOperand::createImm(64 - imm));
5738
5739 return S;
5740 }
5741
DecodeVCVTQ(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5742 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5743 uint64_t Address, const void *Decoder) {
5744 const FeatureBitset &featureBits =
5745 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5746 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5747
5748 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5749 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5750 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5751 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5752 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5753 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5754 unsigned op = fieldFromInstruction(Insn, 5, 1);
5755
5756 DecodeStatus S = MCDisassembler::Success;
5757
5758 // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5759 if (!(imm & 0x38)) {
5760 if (cmode == 0xF) {
5761 if (op == 1) return MCDisassembler::Fail;
5762 Inst.setOpcode(ARM::VMOVv4f32);
5763 }
5764 if (hasFullFP16) {
5765 if (cmode == 0xE) {
5766 if (op == 1) {
5767 Inst.setOpcode(ARM::VMOVv2i64);
5768 } else {
5769 Inst.setOpcode(ARM::VMOVv16i8);
5770 }
5771 }
5772 if (cmode == 0xD) {
5773 if (op == 1) {
5774 Inst.setOpcode(ARM::VMVNv4i32);
5775 } else {
5776 Inst.setOpcode(ARM::VMOVv4i32);
5777 }
5778 }
5779 if (cmode == 0xC) {
5780 if (op == 1) {
5781 Inst.setOpcode(ARM::VMVNv4i32);
5782 } else {
5783 Inst.setOpcode(ARM::VMOVv4i32);
5784 }
5785 }
5786 }
5787 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5788 }
5789
5790 if (!(imm & 0x20)) return MCDisassembler::Fail;
5791
5792 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5793 return MCDisassembler::Fail;
5794 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5795 return MCDisassembler::Fail;
5796 Inst.addOperand(MCOperand::createImm(64 - imm));
5797
5798 return S;
5799 }
5800
DecodeNEONComplexLane64Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5801 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
5802 unsigned Insn,
5803 uint64_t Address,
5804 const void *Decoder) {
5805 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5806 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5807 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5808 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5809 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5810 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5811 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5812 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5813
5814 DecodeStatus S = MCDisassembler::Success;
5815
5816 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5817
5818 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5819 return MCDisassembler::Fail;
5820 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5821 return MCDisassembler::Fail;
5822 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5823 return MCDisassembler::Fail;
5824 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5825 return MCDisassembler::Fail;
5826 // The lane index does not have any bits in the encoding, because it can only
5827 // be 0.
5828 Inst.addOperand(MCOperand::createImm(0));
5829 Inst.addOperand(MCOperand::createImm(rotate));
5830
5831 return S;
5832 }
5833
DecodeLDR(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5834 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5835 uint64_t Address, const void *Decoder) {
5836 DecodeStatus S = MCDisassembler::Success;
5837
5838 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5839 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5840 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5841 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5842 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5843
5844 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5845 S = MCDisassembler::SoftFail;
5846
5847 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5848 return MCDisassembler::Fail;
5849 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5850 return MCDisassembler::Fail;
5851 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5852 return MCDisassembler::Fail;
5853 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5854 return MCDisassembler::Fail;
5855 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5856 return MCDisassembler::Fail;
5857
5858 return S;
5859 }
5860
DecoderForMRRC2AndMCRR2(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5861 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
5862 uint64_t Address, const void *Decoder) {
5863 DecodeStatus S = MCDisassembler::Success;
5864
5865 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5866 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5867 unsigned cop = fieldFromInstruction(Val, 8, 4);
5868 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5869 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5870
5871 if ((cop & ~0x1) == 0xa)
5872 return MCDisassembler::Fail;
5873
5874 if (Rt == Rt2)
5875 S = MCDisassembler::SoftFail;
5876
5877 // We have to check if the instruction is MRRC2
5878 // or MCRR2 when constructing the operands for
5879 // Inst. Reason is because MRRC2 stores to two
5880 // registers so it's tablegen desc has has two
5881 // outputs whereas MCRR doesn't store to any
5882 // registers so all of it's operands are listed
5883 // as inputs, therefore the operand order for
5884 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5885 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5886
5887 if (Inst.getOpcode() == ARM::MRRC2) {
5888 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5889 return MCDisassembler::Fail;
5890 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5891 return MCDisassembler::Fail;
5892 }
5893 Inst.addOperand(MCOperand::createImm(cop));
5894 Inst.addOperand(MCOperand::createImm(opc1));
5895 if (Inst.getOpcode() == ARM::MCRR2) {
5896 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5897 return MCDisassembler::Fail;
5898 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5899 return MCDisassembler::Fail;
5900 }
5901 Inst.addOperand(MCOperand::createImm(CRm));
5902
5903 return S;
5904 }
5905
DecodeForVMRSandVMSR(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5906 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5907 uint64_t Address,
5908 const void *Decoder) {
5909 const FeatureBitset &featureBits =
5910 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5911 DecodeStatus S = MCDisassembler::Success;
5912
5913 // Add explicit operand for the destination sysreg, for cases where
5914 // we have to model it for code generation purposes.
5915 switch (Inst.getOpcode()) {
5916 case ARM::VMSR_FPSCR_NZCVQC:
5917 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5918 break;
5919 case ARM::VMSR_P0:
5920 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5921 break;
5922 }
5923
5924 if (Inst.getOpcode() != ARM::FMSTAT) {
5925 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5926
5927 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5928 if (Rt == 13 || Rt == 15)
5929 S = MCDisassembler::SoftFail;
5930 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5931 } else
5932 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
5933 }
5934
5935 // Add explicit operand for the source sysreg, similarly to above.
5936 switch (Inst.getOpcode()) {
5937 case ARM::VMRS_FPSCR_NZCVQC:
5938 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5939 break;
5940 case ARM::VMRS_P0:
5941 Inst.addOperand(MCOperand::createReg(ARM::VPR));
5942 break;
5943 }
5944
5945 if (featureBits[ARM::ModeThumb]) {
5946 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
5947 Inst.addOperand(MCOperand::createReg(0));
5948 } else {
5949 unsigned pred = fieldFromInstruction(Val, 28, 4);
5950 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5951 return MCDisassembler::Fail;
5952 }
5953
5954 return S;
5955 }
5956
5957 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
DecodeBFLabelOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5958 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
5959 uint64_t Address,
5960 const void *Decoder) {
5961 DecodeStatus S = MCDisassembler::Success;
5962 if (Val == 0 && !zeroPermitted)
5963 S = MCDisassembler::Fail;
5964
5965 uint64_t DecVal;
5966 if (isSigned)
5967 DecVal = SignExtend32<size + 1>(Val << 1);
5968 else
5969 DecVal = (Val << 1);
5970
5971 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
5972 Decoder))
5973 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
5974 return S;
5975 }
5976
DecodeBFAfterTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5977 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
5978 uint64_t Address,
5979 const void *Decoder) {
5980
5981 uint64_t LocImm = Inst.getOperand(0).getImm();
5982 Val = LocImm + (2 << Val);
5983 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
5984 Decoder))
5985 Inst.addOperand(MCOperand::createImm(Val));
5986 return MCDisassembler::Success;
5987 }
5988
DecodePredNoALOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)5989 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
5990 uint64_t Address,
5991 const void *Decoder) {
5992 if (Val >= ARMCC::AL) // also exclude the non-condition NV
5993 return MCDisassembler::Fail;
5994 Inst.addOperand(MCOperand::createImm(Val));
5995 return MCDisassembler::Success;
5996 }
5997
DecodeLOLoop(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)5998 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
5999 const void *Decoder) {
6000 DecodeStatus S = MCDisassembler::Success;
6001
6002 if (Inst.getOpcode() == ARM::MVE_LCTP)
6003 return S;
6004
6005 unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
6006 fieldFromInstruction(Insn, 1, 10) << 1;
6007 switch (Inst.getOpcode()) {
6008 case ARM::t2LEUpdate:
6009 case ARM::MVE_LETP:
6010 Inst.addOperand(MCOperand::createReg(ARM::LR));
6011 Inst.addOperand(MCOperand::createReg(ARM::LR));
6012 LLVM_FALLTHROUGH;
6013 case ARM::t2LE:
6014 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>(
6015 Inst, Imm, Address, Decoder)))
6016 return MCDisassembler::Fail;
6017 break;
6018 case ARM::t2WLS:
6019 case ARM::MVE_WLSTP_8:
6020 case ARM::MVE_WLSTP_16:
6021 case ARM::MVE_WLSTP_32:
6022 case ARM::MVE_WLSTP_64:
6023 Inst.addOperand(MCOperand::createReg(ARM::LR));
6024 if (!Check(S,
6025 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
6026 Address, Decoder)) ||
6027 !Check(S, DecodeBFLabelOperand<false, false, true, 11>(
6028 Inst, Imm, Address, Decoder)))
6029 return MCDisassembler::Fail;
6030 break;
6031 case ARM::t2DLS:
6032 case ARM::MVE_DLSTP_8:
6033 case ARM::MVE_DLSTP_16:
6034 case ARM::MVE_DLSTP_32:
6035 case ARM::MVE_DLSTP_64:
6036 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6037 if (Rn == 0xF) {
6038 // Enforce all the rest of the instruction bits in LCTP, which
6039 // won't have been reliably checked based on LCTP's own tablegen
6040 // record, because we came to this decode by a roundabout route.
6041 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
6042 if ((Insn & ~SBZMask) != CanonicalLCTP)
6043 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail
6044 if (Insn != CanonicalLCTP)
6045 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
6046
6047 Inst.setOpcode(ARM::MVE_LCTP);
6048 } else {
6049 Inst.addOperand(MCOperand::createReg(ARM::LR));
6050 if (!Check(S, DecoderGPRRegisterClass(Inst,
6051 fieldFromInstruction(Insn, 16, 4),
6052 Address, Decoder)))
6053 return MCDisassembler::Fail;
6054 }
6055 break;
6056 }
6057 return S;
6058 }
6059
DecodeLongShiftOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6060 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
6061 uint64_t Address,
6062 const void *Decoder) {
6063 DecodeStatus S = MCDisassembler::Success;
6064
6065 if (Val == 0)
6066 Val = 32;
6067
6068 Inst.addOperand(MCOperand::createImm(Val));
6069
6070 return S;
6071 }
6072
DecodetGPROddRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)6073 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
6074 uint64_t Address, const void *Decoder) {
6075 if ((RegNo) + 1 > 11)
6076 return MCDisassembler::Fail;
6077
6078 unsigned Register = GPRDecoderTable[(RegNo) + 1];
6079 Inst.addOperand(MCOperand::createReg(Register));
6080 return MCDisassembler::Success;
6081 }
6082
DecodetGPREvenRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)6083 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
6084 uint64_t Address, const void *Decoder) {
6085 if ((RegNo) > 14)
6086 return MCDisassembler::Fail;
6087
6088 unsigned Register = GPRDecoderTable[(RegNo)];
6089 Inst.addOperand(MCOperand::createReg(Register));
6090 return MCDisassembler::Success;
6091 }
6092
6093 static DecodeStatus
DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)6094 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
6095 uint64_t Address, const void *Decoder) {
6096 if (RegNo == 15) {
6097 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
6098 return MCDisassembler::Success;
6099 }
6100
6101 unsigned Register = GPRDecoderTable[RegNo];
6102 Inst.addOperand(MCOperand::createReg(Register));
6103
6104 if (RegNo == 13)
6105 return MCDisassembler::SoftFail;
6106
6107 return MCDisassembler::Success;
6108 }
6109
DecodeVSCCLRM(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)6110 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
6111 const void *Decoder) {
6112 DecodeStatus S = MCDisassembler::Success;
6113
6114 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6115 Inst.addOperand(MCOperand::createReg(0));
6116 if (Inst.getOpcode() == ARM::VSCCLRMD) {
6117 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) |
6118 (fieldFromInstruction(Insn, 12, 4) << 8) |
6119 (fieldFromInstruction(Insn, 22, 1) << 12);
6120 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
6121 return MCDisassembler::Fail;
6122 }
6123 } else {
6124 unsigned reglist = fieldFromInstruction(Insn, 0, 8) |
6125 (fieldFromInstruction(Insn, 22, 1) << 8) |
6126 (fieldFromInstruction(Insn, 12, 4) << 9);
6127 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) {
6128 return MCDisassembler::Fail;
6129 }
6130 }
6131 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6132
6133 return S;
6134 }
6135
DecodeMQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)6136 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6137 uint64_t Address,
6138 const void *Decoder) {
6139 if (RegNo > 7)
6140 return MCDisassembler::Fail;
6141
6142 unsigned Register = QPRDecoderTable[RegNo];
6143 Inst.addOperand(MCOperand::createReg(Register));
6144 return MCDisassembler::Success;
6145 }
6146
6147 static const uint16_t QQPRDecoderTable[] = {
6148 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4,
6149 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7
6150 };
6151
DecodeQQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)6152 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6153 uint64_t Address,
6154 const void *Decoder) {
6155 if (RegNo > 6)
6156 return MCDisassembler::Fail;
6157
6158 unsigned Register = QQPRDecoderTable[RegNo];
6159 Inst.addOperand(MCOperand::createReg(Register));
6160 return MCDisassembler::Success;
6161 }
6162
6163 static const uint16_t QQQQPRDecoderTable[] = {
6164 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5,
6165 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7
6166 };
6167
DecodeQQQQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)6168 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6169 uint64_t Address,
6170 const void *Decoder) {
6171 if (RegNo > 4)
6172 return MCDisassembler::Fail;
6173
6174 unsigned Register = QQQQPRDecoderTable[RegNo];
6175 Inst.addOperand(MCOperand::createReg(Register));
6176 return MCDisassembler::Success;
6177 }
6178
DecodeVPTMaskOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6179 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
6180 uint64_t Address,
6181 const void *Decoder) {
6182 DecodeStatus S = MCDisassembler::Success;
6183
6184 // Parse VPT mask and encode it in the MCInst as an immediate with the same
6185 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and
6186 // 't' as 0 and finish with a 1.
6187 unsigned Imm = 0;
6188 // We always start with a 't'.
6189 unsigned CurBit = 0;
6190 for (int i = 3; i >= 0; --i) {
6191 // If the bit we are looking at is not the same as last one, invert the
6192 // CurBit, if it is the same leave it as is.
6193 CurBit ^= (Val >> i) & 1U;
6194
6195 // Encode the CurBit at the right place in the immediate.
6196 Imm |= (CurBit << i);
6197
6198 // If we are done, finish the encoding with a 1.
6199 if ((Val & ~(~0U << i)) == 0) {
6200 Imm |= 1U << i;
6201 break;
6202 }
6203 }
6204
6205 Inst.addOperand(MCOperand::createImm(Imm));
6206
6207 return S;
6208 }
6209
DecodeVpredROperand(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)6210 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
6211 uint64_t Address, const void *Decoder) {
6212 // The vpred_r operand type includes an MQPR register field derived
6213 // from the encoding. But we don't actually want to add an operand
6214 // to the MCInst at this stage, because AddThumbPredicate will do it
6215 // later, and will infer the register number from the TIED_TO
6216 // constraint. So this is a deliberately empty decoder method that
6217 // will inhibit the auto-generated disassembly code from adding an
6218 // operand at all.
6219 return MCDisassembler::Success;
6220 }
6221
DecodeRestrictedIPredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6222 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst,
6223 unsigned Val,
6224 uint64_t Address,
6225 const void *Decoder) {
6226 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
6227 return MCDisassembler::Success;
6228 }
6229
DecodeRestrictedSPredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6230 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst,
6231 unsigned Val,
6232 uint64_t Address,
6233 const void *Decoder) {
6234 unsigned Code;
6235 switch (Val & 0x3) {
6236 case 0:
6237 Code = ARMCC::GE;
6238 break;
6239 case 1:
6240 Code = ARMCC::LT;
6241 break;
6242 case 2:
6243 Code = ARMCC::GT;
6244 break;
6245 case 3:
6246 Code = ARMCC::LE;
6247 break;
6248 }
6249 Inst.addOperand(MCOperand::createImm(Code));
6250 return MCDisassembler::Success;
6251 }
6252
DecodeRestrictedUPredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6253 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst,
6254 unsigned Val,
6255 uint64_t Address,
6256 const void *Decoder) {
6257 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
6258 return MCDisassembler::Success;
6259 }
6260
DecodeRestrictedFPPredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6261 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val,
6262 uint64_t Address,
6263 const void *Decoder) {
6264 unsigned Code;
6265 switch (Val) {
6266 default:
6267 return MCDisassembler::Fail;
6268 case 0:
6269 Code = ARMCC::EQ;
6270 break;
6271 case 1:
6272 Code = ARMCC::NE;
6273 break;
6274 case 4:
6275 Code = ARMCC::GE;
6276 break;
6277 case 5:
6278 Code = ARMCC::LT;
6279 break;
6280 case 6:
6281 Code = ARMCC::GT;
6282 break;
6283 case 7:
6284 Code = ARMCC::LE;
6285 break;
6286 }
6287
6288 Inst.addOperand(MCOperand::createImm(Code));
6289 return MCDisassembler::Success;
6290 }
6291
DecodeVCVTImmOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6292 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
6293 uint64_t Address, const void *Decoder) {
6294 DecodeStatus S = MCDisassembler::Success;
6295
6296 unsigned DecodedVal = 64 - Val;
6297
6298 switch (Inst.getOpcode()) {
6299 case ARM::MVE_VCVTf16s16_fix:
6300 case ARM::MVE_VCVTs16f16_fix:
6301 case ARM::MVE_VCVTf16u16_fix:
6302 case ARM::MVE_VCVTu16f16_fix:
6303 if (DecodedVal > 16)
6304 return MCDisassembler::Fail;
6305 break;
6306 case ARM::MVE_VCVTf32s32_fix:
6307 case ARM::MVE_VCVTs32f32_fix:
6308 case ARM::MVE_VCVTf32u32_fix:
6309 case ARM::MVE_VCVTu32f32_fix:
6310 if (DecodedVal > 32)
6311 return MCDisassembler::Fail;
6312 break;
6313 }
6314
6315 Inst.addOperand(MCOperand::createImm(64 - Val));
6316
6317 return S;
6318 }
6319
FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)6320 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
6321 switch (Opcode) {
6322 case ARM::VSTR_P0_off:
6323 case ARM::VSTR_P0_pre:
6324 case ARM::VSTR_P0_post:
6325 case ARM::VLDR_P0_off:
6326 case ARM::VLDR_P0_pre:
6327 case ARM::VLDR_P0_post:
6328 return ARM::P0;
6329 default:
6330 return 0;
6331 }
6332 }
6333
6334 template<bool Writeback>
DecodeVSTRVLDR_SYSREG(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6335 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
6336 uint64_t Address,
6337 const void *Decoder) {
6338 switch (Inst.getOpcode()) {
6339 case ARM::VSTR_FPSCR_pre:
6340 case ARM::VSTR_FPSCR_NZCVQC_pre:
6341 case ARM::VLDR_FPSCR_pre:
6342 case ARM::VLDR_FPSCR_NZCVQC_pre:
6343 case ARM::VSTR_FPSCR_off:
6344 case ARM::VSTR_FPSCR_NZCVQC_off:
6345 case ARM::VLDR_FPSCR_off:
6346 case ARM::VLDR_FPSCR_NZCVQC_off:
6347 case ARM::VSTR_FPSCR_post:
6348 case ARM::VSTR_FPSCR_NZCVQC_post:
6349 case ARM::VLDR_FPSCR_post:
6350 case ARM::VLDR_FPSCR_NZCVQC_post:
6351 const FeatureBitset &featureBits =
6352 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6353
6354 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
6355 return MCDisassembler::Fail;
6356 }
6357
6358 DecodeStatus S = MCDisassembler::Success;
6359 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
6360 Inst.addOperand(MCOperand::createReg(Sysreg));
6361 unsigned Rn = fieldFromInstruction(Val, 16, 4);
6362 unsigned addr = fieldFromInstruction(Val, 0, 7) |
6363 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6364
6365 if (Writeback) {
6366 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
6367 return MCDisassembler::Fail;
6368 }
6369 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
6370 return MCDisassembler::Fail;
6371
6372 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6373 Inst.addOperand(MCOperand::createReg(0));
6374
6375 return S;
6376 }
6377
DecodeMVE_MEM_pre(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder,unsigned Rn,OperandDecoder RnDecoder,OperandDecoder AddrDecoder)6378 static inline DecodeStatus DecodeMVE_MEM_pre(
6379 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder,
6380 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
6381 DecodeStatus S = MCDisassembler::Success;
6382
6383 unsigned Qd = fieldFromInstruction(Val, 13, 3);
6384 unsigned addr = fieldFromInstruction(Val, 0, 7) |
6385 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6386
6387 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
6388 return MCDisassembler::Fail;
6389 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6390 return MCDisassembler::Fail;
6391 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
6392 return MCDisassembler::Fail;
6393
6394 return S;
6395 }
6396
6397 template <int shift>
DecodeMVE_MEM_1_pre(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6398 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
6399 uint64_t Address, const void *Decoder) {
6400 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6401 fieldFromInstruction(Val, 16, 3),
6402 DecodetGPRRegisterClass,
6403 DecodeTAddrModeImm7<shift>);
6404 }
6405
6406 template <int shift>
DecodeMVE_MEM_2_pre(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6407 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
6408 uint64_t Address, const void *Decoder) {
6409 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6410 fieldFromInstruction(Val, 16, 4),
6411 DecoderGPRRegisterClass,
6412 DecodeT2AddrModeImm7<shift,1>);
6413 }
6414
6415 template <int shift>
DecodeMVE_MEM_3_pre(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6416 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
6417 uint64_t Address, const void *Decoder) {
6418 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6419 fieldFromInstruction(Val, 17, 3),
6420 DecodeMQPRRegisterClass,
6421 DecodeMveAddrModeQ<shift>);
6422 }
6423
6424 template<unsigned MinLog, unsigned MaxLog>
DecodePowerTwoOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6425 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
6426 uint64_t Address,
6427 const void *Decoder) {
6428 DecodeStatus S = MCDisassembler::Success;
6429
6430 if (Val < MinLog || Val > MaxLog)
6431 return MCDisassembler::Fail;
6432
6433 Inst.addOperand(MCOperand::createImm(1LL << Val));
6434 return S;
6435 }
6436
6437 template<unsigned start>
DecodeMVEPairVectorIndexOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)6438 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
6439 uint64_t Address,
6440 const void *Decoder) {
6441 DecodeStatus S = MCDisassembler::Success;
6442
6443 Inst.addOperand(MCOperand::createImm(start + Val));
6444
6445 return S;
6446 }
6447
DecodeMVEVMOVQtoDReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)6448 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
6449 uint64_t Address, const void *Decoder) {
6450 DecodeStatus S = MCDisassembler::Success;
6451 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6452 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
6453 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6454 fieldFromInstruction(Insn, 13, 3));
6455 unsigned index = fieldFromInstruction(Insn, 4, 1);
6456
6457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6458 return MCDisassembler::Fail;
6459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6460 return MCDisassembler::Fail;
6461 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6462 return MCDisassembler::Fail;
6463 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6464 return MCDisassembler::Fail;
6465 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6466 return MCDisassembler::Fail;
6467
6468 return S;
6469 }
6470
DecodeMVEVMOVDRegtoQ(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)6471 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
6472 uint64_t Address, const void *Decoder) {
6473 DecodeStatus S = MCDisassembler::Success;
6474 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6475 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
6476 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6477 fieldFromInstruction(Insn, 13, 3));
6478 unsigned index = fieldFromInstruction(Insn, 4, 1);
6479
6480 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6481 return MCDisassembler::Fail;
6482 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6483 return MCDisassembler::Fail;
6484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6485 return MCDisassembler::Fail;
6486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6487 return MCDisassembler::Fail;
6488 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6489 return MCDisassembler::Fail;
6490 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6491 return MCDisassembler::Fail;
6492
6493 return S;
6494 }
6495
DecodeMVEOverlappingLongShift(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)6496 static DecodeStatus DecodeMVEOverlappingLongShift(
6497 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {
6498 DecodeStatus S = MCDisassembler::Success;
6499
6500 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
6501 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
6502 unsigned Rm = fieldFromInstruction(Insn, 12, 4);
6503
6504 if (RdaHi == 14) {
6505 // This value of RdaHi (really indicating pc, because RdaHi has to
6506 // be an odd-numbered register, so the low bit will be set by the
6507 // decode function below) indicates that we must decode as SQRSHR
6508 // or UQRSHL, which both have a single Rda register field with all
6509 // four bits.
6510 unsigned Rda = fieldFromInstruction(Insn, 16, 4);
6511
6512 switch (Inst.getOpcode()) {
6513 case ARM::MVE_ASRLr:
6514 case ARM::MVE_SQRSHRL:
6515 Inst.setOpcode(ARM::MVE_SQRSHR);
6516 break;
6517 case ARM::MVE_LSLLr:
6518 case ARM::MVE_UQRSHLL:
6519 Inst.setOpcode(ARM::MVE_UQRSHL);
6520 break;
6521 default:
6522 llvm_unreachable("Unexpected starting opcode!");
6523 }
6524
6525 // Rda as output parameter
6526 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6527 return MCDisassembler::Fail;
6528
6529 // Rda again as input parameter
6530 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6531 return MCDisassembler::Fail;
6532
6533 // Rm, the amount to shift by
6534 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6535 return MCDisassembler::Fail;
6536
6537 if (fieldFromInstruction (Insn, 6, 3) != 4)
6538 return MCDisassembler::SoftFail;
6539
6540 if (Rda == Rm)
6541 return MCDisassembler::SoftFail;
6542
6543 return S;
6544 }
6545
6546 // Otherwise, we decode as whichever opcode our caller has already
6547 // put into Inst. Those all look the same:
6548
6549 // RdaLo,RdaHi as output parameters
6550 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6551 return MCDisassembler::Fail;
6552 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6553 return MCDisassembler::Fail;
6554
6555 // RdaLo,RdaHi again as input parameters
6556 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6557 return MCDisassembler::Fail;
6558 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6559 return MCDisassembler::Fail;
6560
6561 // Rm, the amount to shift by
6562 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6563 return MCDisassembler::Fail;
6564
6565 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
6566 Inst.getOpcode() == ARM::MVE_UQRSHLL) {
6567 unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
6568 // Saturate, the bit position for saturation
6569 Inst.addOperand(MCOperand::createImm(Saturate));
6570 }
6571
6572 return S;
6573 }
6574
DecodeMVEVCVTt1fp(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)6575 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
6576 const void *Decoder) {
6577 DecodeStatus S = MCDisassembler::Success;
6578 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6579 fieldFromInstruction(Insn, 13, 3));
6580 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
6581 fieldFromInstruction(Insn, 1, 3));
6582 unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
6583
6584 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6585 return MCDisassembler::Fail;
6586 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6587 return MCDisassembler::Fail;
6588 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
6589 return MCDisassembler::Fail;
6590
6591 return S;
6592 }
6593
6594 template<bool scalar, OperandDecoder predicate_decoder>
DecodeMVEVCMP(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)6595 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
6596 const void *Decoder) {
6597 DecodeStatus S = MCDisassembler::Success;
6598 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6599 unsigned Qn = fieldFromInstruction(Insn, 17, 3);
6600 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
6601 return MCDisassembler::Fail;
6602
6603 unsigned fc;
6604
6605 if (scalar) {
6606 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6607 fieldFromInstruction(Insn, 7, 1) |
6608 fieldFromInstruction(Insn, 5, 1) << 1;
6609 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
6610 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
6611 return MCDisassembler::Fail;
6612 } else {
6613 fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6614 fieldFromInstruction(Insn, 7, 1) |
6615 fieldFromInstruction(Insn, 0, 1) << 1;
6616 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
6617 fieldFromInstruction(Insn, 1, 3);
6618 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6619 return MCDisassembler::Fail;
6620 }
6621
6622 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
6623 return MCDisassembler::Fail;
6624
6625 Inst.addOperand(MCOperand::createImm(ARMVCC::None));
6626 Inst.addOperand(MCOperand::createReg(0));
6627 Inst.addOperand(MCOperand::createImm(0));
6628
6629 return S;
6630 }
6631
DecodeMveVCTP(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)6632 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
6633 const void *Decoder) {
6634 DecodeStatus S = MCDisassembler::Success;
6635 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6636 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6637 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
6638 return MCDisassembler::Fail;
6639 return S;
6640 }
6641
DecodeMVEVPNOT(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)6642 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address,
6643 const void *Decoder) {
6644 DecodeStatus S = MCDisassembler::Success;
6645 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6646 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6647 return S;
6648 }
6649
DecodeT2AddSubSPImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)6650 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
6651 uint64_t Address, const void *Decoder) {
6652 const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
6653 const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6654 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
6655 fieldFromInstruction(Insn, 12, 3) << 8 |
6656 fieldFromInstruction(Insn, 0, 8);
6657 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
6658 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
6659 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
6660 unsigned S = fieldFromInstruction(Insn, 20, 1);
6661 if (sign1 != sign2)
6662 return MCDisassembler::Fail;
6663
6664 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
6665 DecodeStatus DS = MCDisassembler::Success;
6666 if ((!Check(DS,
6667 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
6668 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
6669 return MCDisassembler::Fail;
6670 if (TypeT3) {
6671 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
6672 S = 0;
6673 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
6674 } else {
6675 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
6676 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
6677 return MCDisassembler::Fail;
6678 }
6679 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
6680 return MCDisassembler::Fail;
6681
6682 Inst.addOperand(MCOperand::createReg(0)); // pred
6683
6684 return DS;
6685 }
6686