| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Hexagon/ |
| H A D | v6-spill1.ll | 1 ; RUN: llc -march=hexagon -O2 -pipeliner-max-mii=10 < %s | FileCheck %s
7 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
8 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
9 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
10 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
135 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
138 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
141 declare <16 x i32> @llvm.hexagon.V6.vd0() #1
174 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
177 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Hexagon/ |
| H A D | v6-spill1.ll | 1 ; RUN: llc -march=hexagon -O2 -pipeliner-max-mii=10 < %s | FileCheck %s
7 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
8 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
9 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
10 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
135 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
138 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
141 declare <16 x i32> @llvm.hexagon.V6.vd0() #1
174 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
177 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Hexagon/ |
| H A D | v6-spill1.ll | 1 ; RUN: llc -march=hexagon -O2 -pipeliner-max-mii=10 < %s | FileCheck %s
7 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
8 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
9 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
10 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
135 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
138 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
141 declare <16 x i32> @llvm.hexagon.V6.vd0() #1
174 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
177 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Hexagon/ |
| H A D | v6-spill1.ll | 1 ; RUN: llc -march=hexagon -O2 -pipeliner-max-mii=10 < %s | FileCheck %s
7 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
8 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
9 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
10 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
135 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
138 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
141 declare <16 x i32> @llvm.hexagon.V6.vd0() #1
174 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
177 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/ |
| H A D | v6-spill1.ll | 1 ; RUN: llc -march=hexagon -O2 -pipeliner-max-mii=10 < %s | FileCheck %s
7 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
8 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
9 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
10 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
135 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
138 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
141 declare <16 x i32> @llvm.hexagon.V6.vd0() #1
174 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
177 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Hexagon/ |
| H A D | v6-spill1.ll | 1 ; RUN: llc -march=hexagon -O2 -pipeliner-max-mii=10 < %s | FileCheck %s
7 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
8 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
9 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
10 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
135 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
138 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
141 declare <16 x i32> @llvm.hexagon.V6.vd0() #1
174 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
177 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Hexagon/ |
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v6vect-spill-kill.ll | 1 ; RUN: llc -march=hexagon -O3 < %s
10 %v0 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> undef)
80 %v64 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v62)
82 %v66 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v63)
83 %v67 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v63)
85 %v69 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v65)
97 declare <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32>) #1
103 declare <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32>, <32 x i32>) #1
118 declare <64 x i32> @llvm.hexagon.V6.vmpyuhv.128B(<32 x i32>, <32 x i32>) #1
121 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Hexagon/ |
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Hexagon/ |
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v6vect-spill-kill.ll | 1 ; RUN: llc -march=hexagon -O3 < %s
10 %v0 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> undef)
80 %v64 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v62)
82 %v66 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v63)
83 %v67 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v63)
85 %v69 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v65)
97 declare <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32>) #1
103 declare <1024 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32>, <32 x i32>) #1
118 declare <64 x i32> @llvm.hexagon.V6.vmpyuhv.128B(<32 x i32>, <32 x i32>) #1
121 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/ |
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v6vect-spill-kill.ll | 1 ; RUN: llc -march=hexagon -O3 < %s
10 %v0 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> undef)
80 %v64 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v62)
82 %v66 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v63)
83 %v67 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v63)
85 %v69 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v65)
97 declare <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32>) #1
103 declare <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32>, <32 x i32>) #1
118 declare <64 x i32> @llvm.hexagon.V6.vmpyuhv.128B(<32 x i32>, <32 x i32>) #1
121 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Hexagon/ |
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/ |
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Hexagon/ |
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
[all …]
|
| H A D | v6vect-spill-kill.ll | 1 ; RUN: llc -march=hexagon -O3 < %s
10 %v0 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> undef)
80 %v64 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v62)
82 %v66 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v63)
83 %v67 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v63)
85 %v69 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v65)
97 declare <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32>) #1
103 declare <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32>, <32 x i32>) #1
118 declare <64 x i32> @llvm.hexagon.V6.vmpyuhv.128B(<32 x i32>, <32 x i32>) #1
121 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/ |
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/ |
| H A D | v60-vecpred-spill.ll | 1 ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
6 target triple = "hexagon"
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
139 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
142 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
178 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
181 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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