1; RUN: llc -march=hexagon -O2 < %s | FileCheck %s 2; CHECK-NOT: vmem(r30+#-1){{ *} = v{{[0-9]+}} 3; CHECK-NOT: v{{[0-9]+}} = vmem(r30+#-1) 4; CHECK: v{{[0-9]+}} = vmux 5 6target triple = "hexagon" 7 8; Function Attrs: nounwind 9define void @f0(i8* nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, i16* nocapture %a4, i16* nocapture %a5) #0 { 10b0: 11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3) 12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0) 13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009) 14 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> undef, <16 x i32> undef) 15 %v4 = sdiv i32 %a2, 64 16 %v5 = icmp sgt i32 %a2, 63 17 br i1 %v5, label %b1, label %b6 18 19b1: ; preds = %b0 20 %v6 = bitcast i16* %a5 to <16 x i32>* 21 %v7 = bitcast i16* %a4 to <16 x i32>* 22 %v8 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v3, <16 x i32> %v3) 23 br label %b2 24 25b2: ; preds = %b4, %b1 26 %v9 = phi i32 [ 0, %b1 ], [ %v100, %b4 ] 27 %v10 = phi i8* [ %a0, %b1 ], [ %v87, %b4 ] 28 %v11 = phi <16 x i32>* [ %v6, %b1 ], [ %v99, %b4 ] 29 %v12 = phi <16 x i32>* [ %v7, %b1 ], [ %v95, %b4 ] 30 %v13 = bitcast i8* %v10 to <16 x i32>* 31 %v14 = load <16 x i32>, <16 x i32>* %v13, align 64, !tbaa !0 32 br label %b3 33 34b3: ; preds = %b3, %b2 35 %v15 = phi i32 [ -4, %b2 ], [ %v83, %b3 ] 36 %v16 = phi <32 x i32> [ %v8, %b2 ], [ %v78, %b3 ] 37 %v17 = phi <16 x i32> [ %v3, %b2 ], [ %v82, %b3 ] 38 %v18 = mul nsw i32 %v15, %a1 39 %v19 = getelementptr inbounds i8, i8* %v10, i32 %v18 40 %v20 = bitcast i8* %v19 to <16 x i32>* 41 %v21 = add i32 %v18, -64 42 %v22 = getelementptr inbounds i8, i8* %v10, i32 %v21 43 %v23 = bitcast i8* %v22 to <16 x i32>* 44 %v24 = load <16 x i32>, <16 x i32>* %v23, align 64, !tbaa !0 45 %v25 = load <16 x i32>, <16 x i32>* %v20, align 64, !tbaa !0 46 %v26 = add i32 %v18, 64 47 %v27 = getelementptr inbounds i8, i8* %v10, i32 %v26 48 %v28 = bitcast i8* %v27 to <16 x i32>* 49 %v29 = load <16 x i32>, <16 x i32>* %v28, align 64, !tbaa !0 50 %v30 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v25, <16 x i32> %v14) 51 %v31 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v30, <16 x i32> %v1) 52 %v32 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v31, <16 x i32> %v3, <16 x i32> %v25) 53 %v33 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v16, <16 x i32> %v32, i32 16843009) 54 %v34 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v31, <16 x i32> %v17, <16 x i32> %v2) 55 %v35 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v25, <16 x i32> %v24, i32 1) 56 %v36 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v29, <16 x i32> %v25, i32 1) 57 %v37 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v25, <16 x i32> %v24, i32 2) 58 %v38 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v29, <16 x i32> %v25, i32 2) 59 %v39 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v35, <16 x i32> %v14) 60 %v40 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v36, <16 x i32> %v14) 61 %v41 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v37, <16 x i32> %v14) 62 %v42 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v38, <16 x i32> %v14) 63 %v43 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v39, <16 x i32> %v1) 64 %v44 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v40, <16 x i32> %v1) 65 %v45 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v41, <16 x i32> %v1) 66 %v46 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v42, <16 x i32> %v1) 67 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v43, <16 x i32> %v3, <16 x i32> %v35) 68 %v48 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v44, <16 x i32> %v3, <16 x i32> %v36) 69 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v45, <16 x i32> %v3, <16 x i32> %v37) 70 %v50 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v46, <16 x i32> %v3, <16 x i32> %v38) 71 %v51 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v48, <16 x i32> %v47) 72 %v52 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v33, <32 x i32> %v51, i32 16843009) 73 %v53 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v50, <16 x i32> %v49) 74 %v54 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v52, <32 x i32> %v53, i32 16843009) 75 %v55 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v43, <16 x i32> %v34, <16 x i32> %v2) 76 %v56 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v44, <16 x i32> %v55, <16 x i32> %v2) 77 %v57 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v45, <16 x i32> %v56, <16 x i32> %v2) 78 %v58 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v46, <16 x i32> %v57, <16 x i32> %v2) 79 %v59 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v25, <16 x i32> %v24, i32 3) 80 %v60 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v29, <16 x i32> %v25, i32 3) 81 %v61 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v25, <16 x i32> %v24, i32 4) 82 %v62 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v29, <16 x i32> %v25, i32 4) 83 %v63 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v59, <16 x i32> %v14) 84 %v64 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v60, <16 x i32> %v14) 85 %v65 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v61, <16 x i32> %v14) 86 %v66 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v62, <16 x i32> %v14) 87 %v67 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v63, <16 x i32> %v1) 88 %v68 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v64, <16 x i32> %v1) 89 %v69 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v65, <16 x i32> %v1) 90 %v70 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v66, <16 x i32> %v1) 91 %v71 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v67, <16 x i32> %v3, <16 x i32> %v59) 92 %v72 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v68, <16 x i32> %v3, <16 x i32> %v60) 93 %v73 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v69, <16 x i32> %v3, <16 x i32> %v61) 94 %v74 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v70, <16 x i32> %v3, <16 x i32> %v62) 95 %v75 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v72, <16 x i32> %v71) 96 %v76 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v54, <32 x i32> %v75, i32 16843009) 97 %v77 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v74, <16 x i32> %v73) 98 %v78 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v76, <32 x i32> %v77, i32 16843009) 99 %v79 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v67, <16 x i32> %v58, <16 x i32> %v2) 100 %v80 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v68, <16 x i32> %v79, <16 x i32> %v2) 101 %v81 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v69, <16 x i32> %v80, <16 x i32> %v2) 102 %v82 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v70, <16 x i32> %v81, <16 x i32> %v2) 103 %v83 = add nsw i32 %v15, 1 104 %v84 = icmp eq i32 %v83, 5 105 br i1 %v84, label %b4, label %b3 106 107b4: ; preds = %b3 108 %v85 = phi <16 x i32> [ %v82, %b3 ] 109 %v86 = phi <32 x i32> [ %v78, %b3 ] 110 %v87 = getelementptr inbounds i8, i8* %v10, i32 64 111 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86) 112 %v89 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v86) 113 %v90 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %v88, <16 x i32> %v89, i32 -2) 114 %v91 = tail call <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32> %v85) 115 %v92 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v90) 116 %v93 = getelementptr inbounds <16 x i32>, <16 x i32>* %v12, i32 1 117 store <16 x i32> %v92, <16 x i32>* %v12, align 64, !tbaa !0 118 %v94 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v90) 119 %v95 = getelementptr inbounds <16 x i32>, <16 x i32>* %v12, i32 2 120 store <16 x i32> %v94, <16 x i32>* %v93, align 64, !tbaa !0 121 %v96 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v91) 122 %v97 = getelementptr inbounds <16 x i32>, <16 x i32>* %v11, i32 1 123 store <16 x i32> %v96, <16 x i32>* %v11, align 64, !tbaa !0 124 %v98 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v91) 125 %v99 = getelementptr inbounds <16 x i32>, <16 x i32>* %v11, i32 2 126 store <16 x i32> %v98, <16 x i32>* %v97, align 64, !tbaa !0 127 %v100 = add nsw i32 %v9, 1 128 %v101 = icmp slt i32 %v100, %v4 129 br i1 %v101, label %b2, label %b5 130 131b5: ; preds = %b4 132 br label %b6 133 134b6: ; preds = %b5, %b0 135 ret void 136} 137 138; Function Attrs: nounwind readnone 139declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 140 141; Function Attrs: nounwind readnone 142declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1 143 144; Function Attrs: nounwind readnone 145declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #1 146 147; Function Attrs: nounwind readnone 148declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1 149 150; Function Attrs: nounwind readnone 151declare <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32>, <16 x i32>) #1 152 153; Function Attrs: nounwind readnone 154declare <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32>, <16 x i32>) #1 155 156; Function Attrs: nounwind readnone 157declare <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1>, <16 x i32>, <16 x i32>) #1 158 159; Function Attrs: nounwind readnone 160declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #1 161 162; Function Attrs: nounwind readnone 163declare <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1>, <16 x i32>, <16 x i32>) #1 164 165; Function Attrs: nounwind readnone 166declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #1 167 168; Function Attrs: nounwind readnone 169declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1 170 171; Function Attrs: nounwind readnone 172declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #1 173 174; Function Attrs: nounwind readnone 175declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1 176 177; Function Attrs: nounwind readnone 178declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 179 180; Function Attrs: nounwind readnone 181declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1 182 183; Function Attrs: nounwind readnone 184declare <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32>) #1 185 186attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 187attributes #1 = { nounwind readnone } 188 189!0 = !{!1, !1, i64 0} 190!1 = !{!"omnipotent char", !2, i64 0} 191!2 = !{!"Simple C/C++ TBAA"} 192