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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastTileConfig.cpp173 const TargetSubtargetInfo *ST = &MFunc.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
174 TRI = ST->getRegisterInfo(); in runOnMachineFunction()
H A DX86InstrFPStack.td91 // ST(0) = ST(0) + [mem]
133 // ST(0) = ST(0) + [memint]
568 // CC = ST(0) cmp ST(i)
591 def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
593 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
595 def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop
600 def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
602 def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/GISel/
H A DBPFLegalizerInfo.cpp20 BPFLegalizerInfo::BPFLegalizerInfo(const BPFSubtarget &ST) { in BPFLegalizerInfo() argument
H A DBPFLegalizerInfo.h25 BPFLegalizerInfo(const BPFSubtarget &ST);
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.h174 const GCNSubtarget &ST; variable
255 const GCNSubtarget &ST; variable
388 bool sinkTriviallyRematInsts(const GCNSubtarget &ST,
H A DAMDGPUImageIntrinsicOptimizer.cpp289 const GCNSubtarget &ST = TM->getSubtarget<GCNSubtarget>(F); in imageIntrinsicOptimizerImpl() local
290 if (!AMDGPU::isGFX11Plus(ST) || ST.hasMSAALoadDstSelBug()) in imageIntrinsicOptimizerImpl()
H A DAMDGPULateCodeGenPrepare.cpp98 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in runOnFunction() local
99 if (ST.hasScalarSubwordLoads()) in runOnFunction()
H A DAMDGPUInstCombineIntrinsic.cpp155 simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST, in simplifyAMDGCNImageIntrinsic() argument
228 if (ST->hasD16Images()) { in simplifyAMDGCNImageIntrinsic()
256 if (!ST->hasA16() && !ST->hasG16()) in simplifyAMDGCNImageIntrinsic()
286 if (!OnlyDerivatives && !ST->hasA16()) in simplifyAMDGCNImageIntrinsic()
298 if (OnlyDerivatives && (!ST->hasG16() || ImageDimIntr->GradientStart == in simplifyAMDGCNImageIntrinsic()
826 if (!ST->hasMed3_16()) in instCombineIntrinsic()
982 if (ST->isWave32()) in instCombineIntrinsic()
1173 if (ST->hasDefaultComponentBroadcast()) in instCombineIntrinsic()
1175 else if (ST->hasDefaultComponentZero()) in instCombineIntrinsic()
1191 return simplifyAMDGCNImageIntrinsic(ST, ImageDimIntr, II, IC); in instCombineIntrinsic()
H A DAMDGPUMCInstLower.cpp44 Ctx(ctx), ST(st), AP(ap) { } in AMDGPUMCInstLower()
76 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST)); in lowerOperand()
120 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); in lower()
H A DAMDGPUSetWavePriority.cpp109 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
110 TII = ST.getInstrInfo(); in runOnMachineFunction()
H A DSIOptimizeExecMaskingPreRA.cpp347 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
348 TRI = ST.getRegisterInfo(); in runOnMachineFunction()
349 TII = ST.getInstrInfo(); in runOnMachineFunction()
353 const bool Wave32 = ST.isWave32(); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kLegalizerInfo.h25 M68kLegalizerInfo(const M68kSubtarget &ST);
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCLegalizerInfo.h25 PPCLegalizerInfo(const PPCSubtarget &ST);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp122 const TargetSubtargetInfo &ST = mf.getSubtarget(); in ScheduleDAGInstrs() local
123 SchedModel.init(&ST); in ScheduleDAGInstrs()
244 const TargetSubtargetInfo &ST = MF.getSubtarget(); in addPhysRegDataDeps() local
285 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOpIdx, Dep); in addPhysRegDataDeps()
302 const TargetSubtargetInfo &ST = MF.getSubtarget(); in addPhysRegDeps() local
326 ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep); in addPhysRegDeps()
440 const TargetSubtargetInfo &ST = MF.getSubtarget(); in addVRegDefDeps() local
456 ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep); in addVRegDefDeps()
742 const TargetSubtargetInfo &ST = MF.getSubtarget(); in buildSchedGraph() local
744 : ST.useAA(); in buildSchedGraph()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FalkorHWPFFix.cpp119 const AArch64Subtarget *ST = in runOnFunction() local
121 if (ST->getProcFamily() != AArch64Subtarget::Falkor) in runOnFunction()
814 auto &ST = Fn.getSubtarget<AArch64Subtarget>(); in runOnMachineFunction() local
815 if (ST.getProcFamily() != AArch64Subtarget::Falkor) in runOnMachineFunction()
821 TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo()); in runOnMachineFunction()
822 TRI = ST.getRegisterInfo(); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp130 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>(); in emitThumbRegPlusImmInReg() local
175 } else if (ST.genExecuteOnly()) { in emitThumbRegPlusImmInReg()
176 if (ST.useMovt()) { in emitThumbRegPlusImmInReg()
494 auto &ST = MF.getSubtarget<ARMSubtarget>(); in rewriteFrameIndex() local
499 } else if (ST.genExecuteOnly()) { in rewriteFrameIndex()
511 else if (!ST.useMovt() && CanMakeBottomByteZero) in rewriteFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfDebug.h891 unsigned getStringTypeLoc(const DIStringType *ST) const { in getStringTypeLoc() argument
892 return StringTypeLocMap.lookup(ST); in getStringTypeLoc()
895 void addStringTypeLoc(const DIStringType *ST, unsigned Loc) { in addStringTypeLoc() argument
896 assert(ST); in addStringTypeLoc()
898 StringTypeLocMap[ST] = Loc; in addStringTypeLoc()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVGatherScatterLowering.cpp37 const RISCVSubtarget *ST = nullptr; member in __anonaefb02230111::RISCVGatherScatterLowering
527 ST = &TM.getSubtarget<RISCVSubtarget>(F); in runOnFunction()
528 if (!ST->hasVInstructions() || !ST->useRVVForFixedLengthVectors()) in runOnFunction()
531 TLI = ST->getTargetLowering(); in runOnFunction()
H A DRISCVMergeBaseOffset.cpp29 const RISCVSubtarget *ST = nullptr; member in __anona89a439d0111::RISCVMergeBaseOffsetOpt
215 if (!ST->is64Bit() || OffsetTail.getOpcode() == RISCV::ADDIW) in foldLargeOffset()
461 if (!ST->is64Bit()) in foldIntoMemoryOps()
513 ST = &Fn.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction()
/freebsd/contrib/sendmail/
H A DCACerts14 …Issuer: C=US, ST=California, L=Berkeley, O=Endmail Org, OU=MTA, CN=CA/emailAddress=ca+ca-rsa2021@e…
18 …Subject: C=US, ST=California, L=Berkeley, O=Endmail Org, OU=MTA, CN=CA/emailAddress=ca+ca-rsa2021@…
47 …DirName:/C=US/ST=California/L=Berkeley/O=Endmail Org/OU=MTA/CN=CA/emailAddress=ca+ca-rsa2021@esmtp…
/freebsd/secure/caroot/trusted/
H A DTrustwave_Global_ECC_P256_Certification_Authority.pem20 …Issuer: C = US, ST = Illinois, L = Chicago, O = "Trustwave Holdings, Inc.", CN = Trustwave Global …
24 …Subject: C = US, ST = Illinois, L = Chicago, O = "Trustwave Holdings, Inc.", CN = Trustwave Global…
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16FrameLowering.cpp173 llvm::createMips16FrameLowering(const MipsSubtarget &ST) { in createMips16FrameLowering() argument
174 return new Mips16FrameLowering(ST); in createMips16FrameLowering()
H A DMipsLegalizerInfo.h26 MipsLegalizerInfo(const MipsSubtarget &ST);
/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dst-reset.txt1 *Device-Tree bindings for ST SW reset functionality
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc3-st.txt1 ST DWC3 glue logic
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the

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