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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,apr.yaml59 qcom,glink-channels:
79 qcom,smd-channels:
121 qcom,glink-channels:
127 qcom,glink-channels:
133 - qcom,glink-channels
136 qcom,smd-channels: false
140 - qcom,smd-channels
143 qcom,glink-channels: false
153 qcom,glink-channels = "apr_audio_svc";
190 qcom,glink-channels = "adsp_apps";
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dadc.txt5 - diff-channels : Differential channels muxed for this ADC. The first value
15 diff-channels = <0 1>;
20 diff-channels = <2 3>;
H A Dst,stm32-dfsdm-adc.yaml91 st,adc-channels:
164 - st,adc-channels
178 st,adc-channels:
194 io-channels:
200 - io-channels
210 st,adc-channels:
240 io-channels:
248 - io-channels
300 st,adc-channels = <1>;
309 io-channels = <&dfsdm0 0>;
[all …]
H A Dcc10001_adc.txt11 - adc-reserved-channels: Bitmask of reserved channels,
12 i.e. channels that cannot be used by the OS.
18 adc-reserved-channels = <0x2>;
H A Dcosmic,10001-adc.yaml22 adc-reserved-channels:
25 Bitmask of reserved channels, i.e. channels that cannot be
54 adc-reserved-channels = <0x2>;
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dmmp-dma.txt13 - dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-channels: deprecated
38 dma-channels = <16>;
42 * One irq for all channels
50 dma-channels = <16>;
76 /* One irq for all channels */
H A Dfsl,edma.yaml10 The eDMA channels have multiplex capability by programmable
11 memory-mapped registers. channels are split into two groups, called
49 dma-channels:
73 - dma-channels
92 # defined for the DMA channels.
125 dma-channels:
149 dma-channels:
168 dma-channels = <32>;
182 dma-channels = <32>;
213 dma-channels = <31>;
H A Dapple,admac.yaml13 The controller has been seen with up to 24 channels. Even-numbered channels
14 are TX-only, odd-numbered are RX-only. Individual channels are coupled to
40 dma-channels:
67 - dma-channels
85 dma-channels = <24>;
H A Dsprd-dma.txt11 - dma-channels : Number of DMA channels supported. Should be 32.
16 - #dma-channels : Number of DMA channels supported. Should be 32.
26 dma-channels = <32>;
H A Ddma-common.yaml29 Bitmask of available DMA channels in ascending order that are
32 The first item in the array is for channels 0-31, the second is for
33 channels 32-63, etc.
40 dma-channels:
43 Number of DMA channels supported by the controller.
H A Dste-coh901318.txt10 - #dma-cells: must be set to <1>, as the channels on the
12 - dma-channels: the number of DMA channels handled
22 dma-channels = <40>;
H A Dfsl-mxs-dma.txt6 - interrupts : Should contain the interrupt numbers of DMA channels.
9 - dma-channels : Number of channels supported by the DMA controller
31 dma-channels = <16>;
46 dma-channels = <16>;
H A Dti-edma.txt40 - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
41 these channels will be SW triggered channels. See example.
45 - dma-channel-mask: Mask of usable channels.
46 Single uint32 for EDMA with 32 channels, array of two uint32 for
47 EDMA with 64 channels. See example and
96 ti,edma-memcpy-channels = <20 21>;
99 /* The following channels are reserved: 35-44 */
146 /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
169 * ti,edma-memcpy-channels = <12 13 14 15>;
225 - dma-channels: Specify total DMA channels per CC
H A Dzxdma.txt8 - dma-channels: physical channels supported
9 - dma-requests: virtual channels supported, each virtual channel
22 dma-channels = <24>;
/freebsd/sys/dev/sound/pci/
H A Dhdsp-pcm.c467 pcm[pos * channels + slot]; in buffer_mux_write()
511 pcm[pos * channels + slot] = in buffer_demux_read()
558 unsigned int channels; in buffer_copy() local
571 pos = sndbuf_getreadyptr(ch->buffer) / channels; in buffer_copy()
572 length = sndbuf_getready(ch->buffer) / channels; in buffer_copy()
585 pos = sndbuf_getfreeptr(ch->buffer) / channels; in buffer_copy()
607 slots = hdsp_slot_first_n(slots, channels); in buffer_copy()
613 length - remainder, channels); in buffer_copy()
615 remainder, channels); in buffer_copy()
618 length - remainder, channels); in buffer_copy()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dresistive-adc-touch.yaml14 The device must be connected to an ADC device that provides channels for
24 io-channels:
62 - io-channels
69 io-channels = <&adc 24>, <&adc 25>;
76 io-channels = <&adc 24>, <&adc 25>, <&adc 26>;
83 io-channels = <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Daudio-iio-aux.yaml13 Auxiliary device based on Industrial I/O device channels
22 io-channels:
24 Industrial I/O device channels used
28 Industrial I/O channel names related to io-channels.
51 - io-channels
60 io-channels = <&iio 0>, <&iio 1>, <&iio 2>, <&iio 3>;
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Drenesas,drif.txt15 channels (drifn0 & drifn1). These two internal channels share the common
17 irq, dma channels, address space & clock. This internal split is not
21 The internal channels sharing the CLK & SYNC are tied together by their
26 When both internal channels are enabled they need to be managed together
29 properties of both the internal channels. This channel is identified by a
33 - When both the internal channels that are bonded together are enabled,
34 the zeroth channel is selected as primary-bond. This channels accepts
36 - When only one of the bonded channels need to be enabled, the property
54 - dmas: phandles to the DMA channels.
69 among the bonded channels.
[all …]
/freebsd/sys/contrib/device-tree/src/arm/
H A Dcros-adc-thermistors.dtsi18 io-channels = <&adc 3>;
25 io-channels = <&adc 4>;
32 io-channels = <&adc 5>;
39 io-channels = <&adc 6>;
/freebsd/sys/contrib/device-tree/Bindings/hwmon/
H A Diio-hwmon.yaml20 io-channels:
24 List of phandles to ADC channels to read the monitoring values
28 - io-channels
36 io-channels = <&adc 1>, <&adc 2>;
H A Dti,ina3221.yaml43 description: The node contains optional child nodes for three channels.
44 Each child node describes the information of input source. Input channels
45 default to enabled in the chip. Unless channels are explicitly disabled
46 in device-tree, input channels will be enabled.
65 shunt-voltage conversions for the desired channels in order to
74 to use the same shunt-resistor value on all enabled channels. If
77 exclude specific channels from the summation control function.
104 * Input channels are enabled by default in the device and so
/freebsd/contrib/wpa/src/p2p/
H A Dp2p_go_neg.c41 u8 channels; in p2p_peer_channels_check() local
44 ch = &dev->channels; in p2p_peer_channels_check()
64 channels = *pos++; in p2p_peer_channels_check()
69 cl->channels = channels > P2P_MAX_REG_CLASS_CHANNELS ? in p2p_peer_channels_check()
72 pos += channels; in p2p_peer_channels_check()
339 p2p_channels_intersect(&p2p->channels, &peer->channels, in p2p_build_go_neg_resp()
521 p2p_channels_intersect(&p2p->channels, &dev->channels, &tmp); in p2p_go_select_channel()
591 os_memcpy(&p2p->channels, &p2p->cfg->channels, in p2p_check_pref_chan_no_recv()
635 os_memcpy(&p2p->channels, &p2p->cfg->channels, in p2p_check_pref_chan_recv()
724 os_memcpy(&p2p->channels, &p2p->cfg->channels, in p2p_check_pref_chan()
[all …]
/freebsd/sys/dev/sound/pcm/
H A Dfeeder_format.c54 uint32_t ialign, oalign, channels; member
154 info->channels = AFMT_CHANNEL(f->desc->in); in feed_format_init()
157 info->ialign = info->ibps * info->channels; in feed_format_init()
161 info->oalign = info->obps * info->channels; in feed_format_init()
194 info->channels = (uint32_t)value; in feed_format_set()
195 info->ialign = info->ibps * info->channels; in feed_format_set()
196 info->oalign = info->obps * info->channels; in feed_format_set()
242 j *= info->channels; in feed_format_feed()
/freebsd/sys/contrib/device-tree/Bindings/iio/
H A Diio-bindings.txt4 Sources of IIO channels can be represented by any node in the device
53 io-channels: List of phandle and IIO specifier pairs, one pair
61 order as the io-channels property. Consumers drivers
66 IIO channels from this node. Useful for bus nodes to provide
72 io-channels = <&adc 1>, <&ref 0>;
92 io-channels = <&adc 0>, <&adc 1>, <&adc 2>,
100 io-channels = <&adc 10>, <&adc 11>;
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dnvidia,tegra30-timer.txt3 The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
4 running counter, and 5 watchdog modules. The first two channels may also
13 - interrupts : A list of 6 interrupts; one per each of timer channels 1
14 through 5, and one for the shared interrupt for the remaining channels.

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