/netbsd/sys/external/bsd/drm2/dist/drm/i915/ |
H A D | i915_vma.c | 703 size = max_t(typeof(size), size, vma->fence_size); in i915_vma_insert() 704 alignment = max_t(typeof(alignment), in i915_vma_insert()
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H A D | i915_pmu.c | 28 #define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY)
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H A D | i915_debugfs.c | 3703 sseu->eu_per_subslice = max_t(unsigned int, in cherryview_sseu_device_status() 3758 sseu->eu_per_subslice = max_t(unsigned int, in gen10_sseu_device_status() 3817 sseu->eu_per_subslice = max_t(unsigned int, in gen9_sseu_device_status()
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H A D | intel_pm.c | 3036 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5)); in ilk_increase_wm_latency()
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/netbsd/sys/external/bsd/drm2/dist/drm/vmwgfx/ |
H A D | vmwgfx_drv.c | 549 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); in vmw_get_initial_size() 550 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); in vmw_get_initial_size()
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H A D | vmwgfx_surface.c | 1915 start = max_t(size_t, start, res->backup_offset) - res->backup_offset; in vmw_surface_tex_dirty_range_add() 1955 start = max_t(size_t, start, res->backup_offset) - res->backup_offset; in vmw_surface_buf_dirty_range_add() 2104 num_samples = max_t(u32, 1, srf->multisample_count); in vmw_surface_dirty_alloc()
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H A D | vmwgfx_cmdbuf.c | 1040 max_t(size_t, size, man->default_size), in vmw_cmdbuf_reserve_cur()
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H A D | vmwgfx_kms.c | 2888 bb.x2 = max_t(int, bb.x2, clip.x2); in vmw_du_helper_plane_update() 2889 bb.y2 = max_t(int, bb.y2, clip.y2); in vmw_du_helper_plane_update()
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/netbsd/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
H A D | nouveau_nvkm_engine_gr_ctxgf100.c | 1288 atarget = max_t(u32, gr->tpc_total * i / 32, 1); in gf100_grctx_generate_alpha_beta_tables()
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/netbsd/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | si_dpm.h | 895 u32 max_t; member
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H A D | amdgpu_gfx_v6_0.c | 1382 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v6_0_write_harvested_raster_configs() 1383 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v6_0_write_harvested_raster_configs()
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H A D | amdgpu_gfx_v7_0.c | 1682 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs() 1683 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v7_0_write_harvested_raster_configs()
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H A D | amdgpu_gfx_v8_0.c | 3512 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs() 3513 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); in gfx_v8_0_write_harvested_raster_configs()
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H A D | amdgpu_si_dpm.c | 1940 u32 t_max = dte_data->max_t; in si_update_dte_from_pl2() 2606 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); in si_initialize_smc_dte_tables()
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/netbsd/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/mmu/ |
H A D | nouveau_nvkm_subdev_mmu_vmm.c | 1817 align = max_t(u8, align, shift); in nvkm_vmm_get_locked() 1819 align = max_t(u8, align, 12); in nvkm_vmm_get_locked()
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/netbsd/sys/external/bsd/drm2/dist/drm/i915/display/ |
H A D | intel_sdvo.c | 426 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) in intel_sdvo_debug_write() 589 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) in intel_sdvo_read_response()
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H A D | intel_cdclk.c | 2268 max_t(int, min_voltage_level, in bxt_modeset_calc_cdclk()
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H A D | intel_dp.c | 6806 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); in intel_dp_init_panel_power_sequencer()
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/netbsd/sys/external/bsd/drm2/dist/drm/i915/gt/ |
H A D | intel_rps.c | 1101 return max_t(u32, val, 0xc0); in vlv_rps_min_freq()
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H A D | intel_ggtt.c | 643 ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE, in init_ggtt()
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/netbsd/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_si_dpm.c | 1848 u32 t_max = dte_data->max_t; in si_update_dte_from_pl2() 2509 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); in si_initialize_smc_dte_tables()
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