| /qemu/hw/i386/ |
| H A D | vmmouse.c | 99 return (s->status << 16) | s->nb_queue; in vmmouse_get_status()
131 s->queue[s->nb_queue++] = buttons; in vmmouse_mouse_event()
132 s->queue[s->nb_queue++] = x; in vmmouse_mouse_event()
133 s->queue[s->nb_queue++] = y; in vmmouse_mouse_event()
134 s->queue[s->nb_queue++] = dz; in vmmouse_mouse_event()
160 s, s->absolute, in vmmouse_update_handler()
173 s->queue[s->nb_queue++] = VMMOUSE_VERSION; in vmmouse_read_id()
174 s->status = 0; in vmmouse_read_id()
175 vmmouse_update_handler(s, s->absolute); in vmmouse_read_id()
218 memmove(s->queue, &s->queue[size], sizeof(s->queue[0]) * s->nb_queue); in vmmouse_data()
[all …]
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| /qemu/hw/char/ |
| H A D | stm32l4x5_usart.c | 159 if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || in stm32l4x5_update_irq()
174 ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { in stm32l4x5_update_irq()
199 if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { in stm32l4x5_usart_base_receive()
201 FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); in stm32l4x5_usart_base_receive()
206 if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) { in stm32l4x5_usart_base_receive()
215 s->rdr = *buf; in stm32l4x5_usart_base_receive()
235 s->watch_tag = 0; in usart_transmit()
237 if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) { in usart_transmit()
243 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, in usart_transmit()
532 memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s, in stm32l4x5_usart_base_init()
[all …]
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| H A D | goldfish_tty.c | 79 if (s->int_enabled) { in goldfish_tty_cmd()
95 len = s->data_len; in goldfish_tty_cmd()
96 ptr = s->data_ptr; in goldfish_tty_cmd()
109 len = s->data_len; in goldfish_tty_cmd()
110 ptr = s->data_ptr; in goldfish_tty_cmd()
119 if (s->int_enabled && fifo8_is_empty(&s->rx_fifo)) { in goldfish_tty_cmd()
146 s->data_ptr = deposit64(s->data_ptr, 32, 32, value); in goldfish_tty_write()
188 if (s->int_enabled && !fifo8_is_empty(&s->rx_fifo)) { in goldfish_tty_receive()
201 s->data_ptr = 0; in goldfish_tty_reset()
202 s->data_len = 0; in goldfish_tty_reset()
[all …]
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| /qemu/hw/timer/ |
| H A D | cmsdk-apb-timer.c | 73 qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK)); in cmsdk_apb_timer_update()
83 r = s->ctrl; in cmsdk_apb_timer_read()
92 r = s->intstatus; in cmsdk_apb_timer_read()
126 ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); in cmsdk_apb_timer_write()
155 ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); in cmsdk_apb_timer_write()
198 s->ctrl = 0; in cmsdk_apb_timer_reset()
199 s->intstatus = 0; in cmsdk_apb_timer_reset()
212 ptimer_set_period_from_clock(s->timer, s->pclk, 1); in cmsdk_apb_timer_clk_update()
225 s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", in cmsdk_apb_timer_init()
238 s->timer = ptimer_init(cmsdk_apb_timer_tick, s, in cmsdk_apb_timer_realize()
[all …]
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| /qemu/hw/dma/ |
| H A D | xlnx-zdma.c | 213 pending = s->regs[R_ZDMA_CH_ISR] & ~s->regs[R_ZDMA_CH_IMR]; in zdma_ch_imr_update_irq()
341 if (!zdma_load_descriptor(s, src_addr, &s->dsc_src)) { in zdma_load_src_descriptor()
376 if (!zdma_load_descriptor(s, dst_addr, &s->dsc_dst)) { in zdma_load_dst_descriptor()
424 address_space_write(&s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen); in zdma_write_dst()
437 s->dsc_dst.words[2] = FIELD_DP32(s->dsc_dst.words[2], in zdma_write_dst()
484 memcpy(s->buf, &s->regs[R_ZDMA_CH_WR_ONLY_WORD0], s->cfg.bus_width / 8); in zdma_process_descr()
500 address_space_read(&s->dma_as, src_addr, s->attr, s->buf, len); in zdma_process_descr()
507 zdma_write_dst(s, s->buf, len); in zdma_process_descr()
538 while (s->state == ENABLED && !s->error) { in zdma_run()
772 address_space_init(&s->dma_as, s->dma_mr, "zdma-dma"); in zdma_realize()
[all …]
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| H A D | sifive_pdma.c | 119 s->chan[ch].exec_dst = dst; in sifive_pdma_run()
120 s->chan[ch].exec_src = src; in sifive_pdma_run()
277 SiFivePDMAState *s = opaque; in sifive_pdma_read() local
377 s->chan[ch].next_bytes = in sifive_pdma_writel()
381 s->chan[ch].next_bytes = in sifive_pdma_writel()
385 s->chan[ch].next_dst = deposit64(s->chan[ch].next_dst, 0, 32, value); in sifive_pdma_writel()
388 s->chan[ch].next_dst = deposit64(s->chan[ch].next_dst, 32, 32, value); in sifive_pdma_writel()
391 s->chan[ch].next_src = deposit64(s->chan[ch].next_src, 0, 32, value); in sifive_pdma_writel()
394 s->chan[ch].next_src = deposit64(s->chan[ch].next_src, 32, 32, value); in sifive_pdma_writel()
416 SiFivePDMAState *s = opaque; in sifive_pdma_write() local
[all …]
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| /qemu/hw/arm/ |
| H A D | stellaris.c | 101 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
206 return s->int_status & s->int_mask; in ssys_read()
462 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); in stellaris_sys_instance_init()
516 return s->mris & s->mimr; in stellaris_i2c_read()
530 level = (s->mris & s->mimr) != 0; in stellaris_i2c_update()
550 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { in stellaris_i2c_write()
569 s->mdr = i2c_recv(s->bus); in stellaris_i2c_write()
572 i2c_send(s->bus, s->mdr); in stellaris_i2c_write()
761 level = (s->ris & s->im & (1 << n)) != 0; in stellaris_adc_update()
782 s->noise = s->noise * 314159 + 1; in stellaris_adc_trigger()
[all …]
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| H A D | fsl-imx25.c | 37 FslIMX25State *s = FSL_IMX25(obj); in fsl_imx25_init() local
83 FslIMX25State *s = FSL_IMX25(dev); in fsl_imx25_realize() local
94 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, in fsl_imx25_realize()
96 sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, in fsl_imx25_realize()
140 s->gpt[i].ccm = IMX_CCM(&s->ccm); in fsl_imx25_realize()
161 s->epit[i].ccm = IMX_CCM(&s->ccm); in fsl_imx25_realize()
172 object_property_set_uint(OBJECT(&s->fec), "phy-num", s->phy_num, in fsl_imx25_realize()
289 &s->rom[0]); in fsl_imx25_realize()
295 &s->rom[1]); in fsl_imx25_realize()
303 &s->iram); in fsl_imx25_realize()
[all …]
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| H A D | fsl-imx6.c | 42 FslIMX6State *s = FSL_IMX6(obj); in fsl_imx6_init() local
48 object_initialize_child(obj, name, &s->cpu[i], in fsl_imx6_init()
114 FslIMX6State *s = FSL_IMX6(dev); in fsl_imx6_realize() local
200 s->gpt.ccm = IMX_CCM(&s->ccm); in fsl_imx6_realize()
207 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, in fsl_imx6_realize()
221 s->epit[i].ccm = IMX_CCM(&s->ccm); in fsl_imx6_realize()
389 object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, in fsl_imx6_realize()
459 &s->rom); in fsl_imx6_realize()
467 &s->caam); in fsl_imx6_realize()
475 &s->ocram); in fsl_imx6_realize()
[all …]
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| /qemu/block/ |
| H A D | nbd.c | 118 s->conn = NULL; in nbd_clear_bdrvstate()
224 if (s->ioc) { in nbd_teardown_connection()
256 s->open_timer = aio_timer_new(bdrv_get_aio_context(s->bs), in open_timer_init()
328 s->ioc = nbd_co_establish_connection(s->conn, &s->info, blocking, errp); in nbd_co_do_establish_connection()
399 if (s->ioc) { in nbd_reconnect_attempt()
461 ret = nbd_receive_reply(s->bs, s->ioc, &s->reply, s->info.mode, errp); in nbd_receive_replies()
500 qemu_co_queue_wait(&s->free_sema, &s->requests_lock); in nbd_co_send_request()
1865 s->saddr = nbd_config(s, options, errp); in nbd_process_options()
1878 s->tlscreds = nbd_get_tls_creds(s->tlscredsid, errp); in nbd_process_options()
1912 s->bs = bs; in nbd_open()
[all …]
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| H A D | cloop.c | 91 s->block_size = be32_to_cpu(s->block_size); in cloop_open()
117 s->n_blocks = be32_to_cpu(s->n_blocks); in cloop_open()
152 s->offsets[i] = be64_to_cpu(s->offsets[i]); in cloop_open()
157 if (s->offsets[i] < s->offsets[i - 1]) { in cloop_open()
164 size = s->offsets[i] - s->offsets[i - 1]; in cloop_open()
191 s->uncompressed_block = g_try_malloc(s->block_size); in cloop_open()
202 s->current_block = s->n_blocks; in cloop_open()
204 s->sectors_per_block = s->block_size/512; in cloop_open()
236 s->zstream.next_in = s->compressed_block; in cloop_read_block()
238 s->zstream.next_out = s->uncompressed_block; in cloop_read_block()
[all …]
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| H A D | linux-aio.c | 213 while ((s->event_max = io_getevents_advance_and_peek(s->ctx, &events, in qemu_laio_process_completions()
215 for (s->event_idx = 0; s->event_idx < s->event_max; ) { in qemu_laio_process_completions()
234 s->event_max = 0; in qemu_laio_process_completions()
235 s->event_idx = 0; in qemu_laio_process_completions()
328 s->io_q.blocked = (s->io_q.in_queue > 0); in ioq_submit()
365 if (!s->io_q.blocked && !QSIMPLEQ_EMPTY(&s->io_q.pending)) { in laio_deferred_fn()
398 if (s->io_q.in_queue >= laio_max_batch(s, dev_max_batch)) { in laio_do_submit()
455 s = g_malloc0(sizeof(*s)); in laio_init()
470 return s; in laio_init()
475 g_free(s); in laio_init()
[all …]
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| /qemu/hw/display/ |
| H A D | ssd0323.c | 81 s->framebuffer[s->col + s->row * 64] = data; in OBJECT_DECLARE_SIMPLE_TYPE()
84 if (s->row > s->row_end) { in OBJECT_DECLARE_SIMPLE_TYPE()
85 s->row = s->row_start; in OBJECT_DECLARE_SIMPLE_TYPE()
88 if (s->col > s->col_end) { in OBJECT_DECLARE_SIMPLE_TYPE()
89 s->col = s->col_start; in OBJECT_DECLARE_SIMPLE_TYPE()
93 if (s->col > s->col_end) { in OBJECT_DECLARE_SIMPLE_TYPE()
95 s->col = s->col_start; in OBJECT_DECLARE_SIMPLE_TYPE()
97 if (s->row > s->row_end) { in OBJECT_DECLARE_SIMPLE_TYPE()
98 s->row = s->row_start; in OBJECT_DECLARE_SIMPLE_TYPE()
115 s->col = s->col_start = s->cmd_data[0] % 64; in OBJECT_DECLARE_SIMPLE_TYPE()
[all …]
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| /qemu/hw/misc/ |
| H A D | zynq_slcr.c | 358 s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL] in zynq_slcr_reset_init()
361 s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA] in zynq_slcr_reset_init()
386 s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3] in zynq_slcr_reset_init()
392 s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2] in zynq_slcr_reset_init()
394 s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909; in zynq_slcr_reset_init()
399 s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909; in zynq_slcr_reset_init()
400 s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909; in zynq_slcr_reset_init()
403 s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2] in zynq_slcr_reset_init()
407 s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909; in zynq_slcr_reset_init()
412 s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2] in zynq_slcr_reset_init()
[all …]
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| /qemu/hw/i386/kvm/ |
| H A D | apic.c | 91 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); in kvm_get_apic_state()
95 apic_next_timer(s, s->initial_count_load_time); in kvm_get_apic_state()
100 s->apicbase = val; in kvm_apic_set_base()
106 s->tpr = (val & 0x0f) << 4; in kvm_apic_set_tpr()
111 return s->tpr >> 4; in kvm_apic_get_tpr()
144 kvm_put_apicbase(s->cpu, s->apicbase); in kvm_apic_put()
156 run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s)); in kvm_apic_post_load()
179 run_on_cpu(CPU(s->cpu), do_inject_external_nmi, RUN_ON_CPU_HOST_PTR(s)); in kvm_apic_external_nmi()
223 s->wait_for_sipi = 0; in kvm_apic_reset()
225 run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s)); in kvm_apic_reset()
[all …]
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| /qemu/hw/intc/ |
| H A D | bcm2835_ic.c | 47 set = extract64(s->gpu_irq_level, s->fiq_select, 1); in bcm2835_ic_update()
52 set = (s->gpu_irq_level & s->gpu_irq_enable) in bcm2835_ic_update()
53 || (s->arm_irq_level & s->arm_irq_enable); in bcm2835_ic_update()
63 s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0); in bcm2835_ic_set_gpu_irq()
73 s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0); in bcm2835_ic_set_arm_irq()
83 uint64_t gpu_pending = s->gpu_irq_level & s->gpu_irq_enable; in bcm2835_ic_read()
89 res = s->arm_irq_level & s->arm_irq_enable; in bcm2835_ic_read()
107 res = (s->fiq_enable << 7) | s->fiq_select; in bcm2835_ic_read()
196 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); in bcm2835_ic_init()
203 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); in bcm2835_ic_init()
[all …]
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| H A D | omap_intc.c | 75 level = s->bank[j].irqs & ~s->bank[j].mask & in omap_inth_sir_update()
76 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); in omap_inth_sir_update()
97 has_intr |= s->bank[i].irqs & ~s->bank[i].mask & in omap_inth_update()
98 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); in omap_inth_update()
100 if (s->new_agr[is_fiq] & has_intr & s->mask) { in omap_inth_update()
349 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority)); in omap_inth_reset()
360 s->mask = ~0; in omap_inth_reset()
372 s->nbanks = 1; in omap_intc_init()
376 memory_region_init_io(&s->mmio, obj, &omap_inth_mem_ops, s, in omap_intc_init()
629 s->nbanks = 3; in omap2_intc_init()
[all …]
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| H A D | armv7m_nvic.c | 423 return nvic_exec_prio(s) > nvic_pending_prio(s); in armv7m_nvic_can_take_pending_exception()
440 prio &= MAKE_64BIT_MASK(8 - s->num_prio_bits, s->num_prio_bits); in set_prio()
551 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; in do_armv7m_nvic_set_pending()
697 vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; in armv7m_nvic_set_pending_lazyfp()
740 nvic_exec_prio(s) <= exc_group_prio(s, vec->prio, secure)) { in armv7m_nvic_set_pending_lazyfp()
807 exc_targets_secure(s, s->vectpending); in vectpending_targets_secure()
2588 memset(s->vectors, 0, sizeof(s->vectors)); in armv7m_nvic_reset()
2589 memset(s->sec_vectors, 0, sizeof(s->sec_vectors)); in armv7m_nvic_reset()
2635 memset(s->itns, 0, sizeof(s->itns)); in armv7m_nvic_reset()
2678 if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { in armv7m_nvic_realize()
[all …]
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| /qemu/hw/usb/ |
| H A D | hcd-dwc2.c | 70 if ((s->gintsts & s->gintmsk) && (s->gahbcfg & GAHBCFG_GLBL_INTR_EN)) { in dwc2_update_irq()
105 if (s->haint & s->haintmsk) { in dwc2_raise_host_irq()
116 if (!(s->haint & s->haintmsk)) { in dwc2_lower_host_irq()
126 if (s->hreg1[index + 2] & s->hreg1[index + 3]) { in dwc2_update_hc_irq()
136 timer_mod(s->eof_timer, s->sof_time + s->usb_frame_time); in dwc2_eof_timer()
142 s->sof_time += s->usb_frame_time; in dwc2_sof()
160 frcnt = (uint16_t)((now - s->sof_time) / s->fi); in dwc2_frame_boundary()
162 s->hfnum = s->frame_number & HFNUM_MAX_FRNUM; in dwc2_frame_boundary()
1294 memset(s->hreg1, 0, sizeof(s->hreg1)); in dwc2_reset_enter()
1295 memset(s->pcgreg, 0, sizeof(s->pcgreg)); in dwc2_reset_enter()
[all …]
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| H A D | dev-wacom.c | 196 s->dx += dx1; in usb_mouse_event()
212 s->dz += dz; in usb_wacom_event()
243 s->dx -= dx; in usb_mouse_poll()
244 s->dy -= dy; in usb_mouse_poll()
245 s->dz -= dz; in usb_mouse_poll()
307 s->dx = 0; in usb_wacom_handle_reset()
308 s->dy = 0; in usb_wacom_handle_reset()
309 s->dz = 0; in usb_wacom_handle_reset()
310 s->x = 0; in usb_wacom_handle_reset()
311 s->y = 0; in usb_wacom_handle_reset()
[all …]
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| /qemu/hw/audio/ |
| H A D | lm4549.c | 107 written_bytes = AUD_write(s->voice, s->buffer, in lm4549_audio_transfer()
120 s->buffer[i] = s->buffer[i + written_samples]; in lm4549_audio_transfer()
149 (s->data_req_cb)(s->opaque); in lm4549_audio_out_callback()
196 s, in lm4549_write()
234 s->buffer[s->buffer_level++] = (left >> 4); in lm4549_write_samples()
235 s->buffer[s->buffer_level++] = (right >> 4); in lm4549_write_samples()
263 &s->card, in lm4549_post_load()
264 s->voice, in lm4549_post_load()
266 s, in lm4549_post_load()
306 s, in lm4549_init()
[all …]
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| H A D | asc.c | 260 if (s->fifos[0].cnt == 0 && s->fifos[1].cnt == 0) { in generate_fifo()
326 samples = MIN(s->samples, free_b >> s->shift); in asc_out_cb()
357 AUD_write(s->voice, s->silentbuf, samples << s->shift); in asc_out_cb()
362 AUD_write(s->voice, s->mixbuf, generated << s->shift); in asc_out_cb()
619 memset(s->regs, 0, sizeof(s->regs)); in asc_reset_hold()
655 s->voice = AUD_open_out(&s->card, s->voice, "asc.out", s, asc_out_cb, in asc_realize()
657 s->shift = 1; in asc_realize()
658 s->samples = AUD_get_buffer_size_out(s->voice) >> s->shift; in asc_realize()
659 s->mixbuf = g_malloc0(s->samples << s->shift); in asc_realize()
661 s->silentbuf = g_malloc0(s->samples << s->shift); in asc_realize()
[all …]
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| /qemu/hw/gpio/ |
| H A D | max7310.c | 40 s->level &= s->direction; in max7310_reset()
43 s->status = 0x01; in max7310_reset()
53 return s->level ^ s->polarity; in max7310_rx()
56 return s->level & ~s->direction; in max7310_rx()
99 for (diff = (data ^ s->level) & ~s->direction; diff; in max7310_tx()
105 s->level = (s->level & s->direction) | (data & ~s->direction); in max7310_tx()
113 s->level &= ~(s->direction ^ data); in max7310_tx()
135 s->len = 0; in max7310_event()
177 s->level |= s->direction & (1 << line); in max7310_gpio_set()
179 s->level &= ~(s->direction & (1 << line)); in max7310_gpio_set()
[all …]
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| H A D | bcm2838_gpio.c | 111 sdbus_reparent_card(s->sdbus_sdhost, s->sdbus_sdhci); in gpfsel_set()
122 sdbus_reparent_card(s->sdbus_sdhci, s->sdbus_sdhost); in gpfsel_set()
248 gpset(s, value, 0, 32, &s->lev0); in bcm2838_gpio_write()
251 gpset(s, value, 32, 22, &s->lev1); in bcm2838_gpio_write()
254 gpclr(s, value, 0, 32, &s->lev0); in bcm2838_gpio_write()
257 gpclr(s, value, 32, 22, &s->lev1); in bcm2838_gpio_write()
303 memset(s->fsel, 0, sizeof(s->fsel)); in bcm2838_gpio_reset()
308 sdbus_reparent_card(&s->sdbus, s->sdbus_sdhci); in bcm2838_gpio_reset()
310 s->lev0 = 0; in bcm2838_gpio_reset()
313 memset(s->fsel, 0, sizeof(s->fsel)); in bcm2838_gpio_reset()
[all …]
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| /qemu/hw/sh4/ |
| H A D | sh7750.c | 133 return (s->portdira & s->pdtra) | /* CPU */ in porta_lines()
134 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ in porta_lines()
135 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ in porta_lines()
140 return (s->portdirb & s->pdtrb) | /* CPU */ in portb_lines()
141 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ in portb_lines()
142 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ in portb_lines()
159 trace_sh7750_porta(prev, currenta, s->pdtra, s->pctra); in porta_changed()
186 trace_sh7750_portb(prev, currentb, s->pdtrb, s->pctrb); in portb_changed()
774 s->cpu = cpu; in sh7750_init()
776 memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s, in sh7750_init()
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