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Searched refs:val (Results 26 – 50 of 1028) sorted by relevance

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/qemu/hw/net/
H A Deepro100.c660 return val;
949 switch (val) { in eepro100_cu_command()
1099 return val; in eepro100_read_eeprom()
1108 val = SET_MASKED(val, 0x31, eeprom->value); in eepro100_write_eeprom()
1170 return val; in eepro100_read_mdi()
1265 val = (val & 0xffff0000) + data; in eepro100_write_mdi()
1359 val = 0; in eepro100_read1()
1374 return val; in eepro100_read1()
1402 return val; in eepro100_read2()
1434 return val; in eepro100_read4()
[all …]
H A Dne2000.c269 s->cmd = val; in ne2000_ioport_write()
311 s->boundary = val; in ne2000_ioport_write()
315 s->imr = val; in ne2000_ioport_write()
319 s->tpsr = val; in ne2000_ioport_write()
340 s->rxcr = val; in ne2000_ioport_write()
343 s->dcfg = val; in ne2000_ioport_write()
354 s->curpag = val; in ne2000_ioport_write()
438 s->mem[addr] = val; in ne2000_mem_writeb()
637 uint64_t val; in ne2000_read() local
652 trace_ne2000_read(addr, val); in ne2000_read()
[all …]
/qemu/include/hw/pci/
H A Dpci.h408 *config = val; in pci_set_byte()
420 stw_le_p(config, val); in pci_set_word()
432 stl_le_p(config, val); in pci_set_long()
507 return val & mask; in pci_byte_test_and_clear_mask()
515 return val & mask; in pci_byte_test_and_set_mask()
523 return val & mask; in pci_word_test_and_clear_mask()
531 return val & mask; in pci_word_test_and_set_mask()
539 return val & mask; in pci_long_test_and_clear_mask()
547 return val & mask; in pci_long_test_and_set_mask()
555 return val & mask; in pci_quad_test_and_clear_mask()
[all …]
/qemu/hw/pci-host/
H A Ddino.c102 uint32_t val; in dino_chip_read_with_attrs() local
135 val = s->iar0; in dino_chip_read_with_attrs()
138 val = s->iar1; in dino_chip_read_with_attrs()
141 val = s->imr; in dino_chip_read_with_attrs()
144 val = s->icr; in dino_chip_read_with_attrs()
147 val = s->ipr; in dino_chip_read_with_attrs()
152 val = s->ilr; in dino_chip_read_with_attrs()
182 *data = val; in dino_chip_read_with_attrs()
232 s->iar0 = val; in dino_chip_write_with_attrs()
238 s->imr = val; in dino_chip_write_with_attrs()
[all …]
/qemu/target/m68k/
H A Dhelper.c1216 val = ((int64_t)val) >> 40; in HELPER()
1217 if (val != 0 && val != -1) in HELPER()
1220 val = ((int64_t)val) >> 32; in HELPER()
1221 if (val != 0 && val != -1) in HELPER()
1230 (index == 0) ? (int8_t)(val) : ((index == 1) ? (int16_t)(val) : (val)) \
1334 val = (val >> 24) & 0xffffu; in HELPER()
1338 val += (val & 1); in HELPER()
1346 val += (val & 1); in HELPER()
1354 if (val != (uint16_t) val) { in HELPER()
1360 if (val != (uint32_t)val) { in HELPER()
[all …]
/qemu/target/ppc/
H A Dmisc_helper.c54 env->spr[sprn] = val; in helper_spr_core_write_generic()
60 cenv->spr[sprn] = val; in helper_spr_core_write_generic()
69 uint32_t run = val & 1; in helper_spr_write_CTRL()
167 ppc_store_sdr1(env, val); in helper_store_sdr1()
186 if (val & ~ptcr_mask) { in helper_store_ptcr()
189 val &= ptcr_mask; in helper_store_ptcr()
314 if (val & ~0x3f8ULL) { in helper_store_sprc()
352 env->scratch[nr] = val; in do_store_scratch()
358 cenv->scratch[nr] = val; in do_store_scratch()
402 store_40x_dbcr0(env, val); in helper_store_40x_dbcr0()
[all …]
/qemu/hw/dma/
H A Drc4030.c121 uint32_t val; in rc4030_read() local
127 val = s->config; in rc4030_read()
225 val = 0; in rc4030_read()
237 val = 0; in rc4030_read()
247 val = 0; in rc4030_read()
255 return val; in rc4030_read()
262 uint32_t val = data; in rc4030_write() local
432 uint32_t val; in jazzio_read() local
440 val = 0; in jazzio_read()
459 val = 0; in jazzio_read()
[all …]
/qemu/hw/misc/
H A Dedu.c88 edu->irq_status |= val; in edu_raise_irq()
182 *dma = *val; in dma_rw()
184 *val = *dma; in dma_rw()
195 uint64_t val = ~0ULL; in edu_mmio_read() local
198 return val; in edu_mmio_read()
202 return val; in edu_mmio_read()
210 val = edu->addr4; in edu_mmio_read()
214 val = edu->fact; in edu_mmio_read()
237 return val; in edu_mmio_read()
265 edu->fact = val; in edu_mmio_write()
[all …]
H A Dbcm2835_mphi.c42 uint32_t val = 0; in mphi_reg_read() local
46 val = s->outdda; in mphi_reg_read()
49 val = s->outddb; in mphi_reg_read()
52 val = s->ctrl; in mphi_reg_read()
53 val |= 1 << 17; in mphi_reg_read()
59 val = s->swirq; in mphi_reg_read()
62 val = s->swirq; in mphi_reg_read()
69 return val; in mphi_reg_read()
79 s->outdda = val; in mphi_reg_write()
82 s->outddb = val; in mphi_reg_write()
[all …]
/qemu/include/qemu/
H A Dhost-utils.h141 return val ? __builtin_clz(val) - 24 : 8; in clz8()
156 return val ? __builtin_clz(val) - 16 : 16; in clz16()
168 return val ? __builtin_clz(val) : 32; in clz32()
179 return clz32(~val); in clo32()
191 return val ? __builtin_clzll(val) : 64; in clz64()
214 return val ? __builtin_ctz(val) : 8; in ctz8()
226 return val ? __builtin_ctz(val) : 16; in ctz16()
238 return val ? __builtin_ctz(val) : 32; in ctz32()
261 return val ? __builtin_ctzll(val) : 64; in ctz64()
287 return clz32(val ^ ((int32_t)val >> 1)) - 1; in clrsb32()
[all …]
/qemu/hw/usb/
H A Dhcd-dwc2.c58 *(data) = val; \
697 return val; in dwc2_glbreg_read()
776 val = ~val; in dwc2_glbreg_write()
792 *mmio = val; in dwc2_glbreg_write()
814 return val; in dwc2_fszreg_read()
835 *mmio = val; in dwc2_fszreg_write()
869 return val; in dwc2_hreg0_read()
983 return val; in dwc2_hreg1_read()
1024 val = ~val; in dwc2_hreg1_write()
1078 return val; in dwc2_pcgreg_read()
[all …]
/qemu/hw/m68k/
H A Dnext-cube.c266 uint64_t val; in next_mmio_read() local
290 val = 0x7f; in next_mmio_read()
294 val = 0; in next_mmio_read()
299 return val; in next_mmio_read()
357 uint64_t val; in next_scr_readfn() local
372 val = 0x40; in next_scr_readfn()
393 val = 0; in next_scr_readfn()
397 return val; in next_scr_readfn()
595 uint64_t val; in next_dma_read() local
641 val = 0; in next_dma_read()
[all …]
/qemu/target/xtensa/core-dsp3400/
H A Dxtensa-modules.c.inc388 tie_t = (val << 28) >> 28;
404 tie_t = (val << 28) >> 28;
420 tie_t = (val << 28) >> 28;
436 tie_t = (val << 28) >> 28;
452 tie_t = (val << 28) >> 28;
468 tie_t = (val << 28) >> 28;
484 tie_t = (val << 30) >> 30;
500 tie_t = (val << 30) >> 30;
517 tie_t = (val << 28) >> 28;
519 tie_t = (val << 24) >> 28;
[all …]
/qemu/hw/audio/
H A Dvia-ac97.c103 val |= 0x1f; in codec_write()
248 uint64_t val = 0; in sgd_read() local
252 val = s->aur.stat; in sgd_read()
261 val = s->aur.type; in sgd_read()
264 val = s->aur.curr; in sgd_read()
273 val = s->ac97_cmd; in sgd_read()
278 val |= BIT(4); in sgd_read()
281 val |= BIT(8); in sgd_read()
292 return val; in sgd_read()
352 if (val >> 30) { in sgd_write()
[all …]
/qemu/hw/ppc/
H A Dpnv_chiptod.c110 uint64_t val = 0; in pnv_chiptod_xscom_read() local
138 val = 0; in pnv_chiptod_xscom_read()
141 val = chiptod->tod_error; in pnv_chiptod_xscom_read()
145 val |= PPC_BIT(4); in pnv_chiptod_xscom_read()
155 return val; in pnv_chiptod_xscom_read()
238 uint32_t addr = val >> 32; in chiptod_power9_tx_ttype_target()
263 uint32_t addr = val >> 32; in chiptod_power10_tx_ttype_target()
301 val &= ~PPC_BIT(1); in pnv_chiptod_xscom_write()
327 if (!(val & PPC_BIT(0))) { in pnv_chiptod_xscom_write()
330 val); in pnv_chiptod_xscom_write()
[all …]
H A Dpnv_sbe.c91 uint64_t val = 0; in pnv_sbe_power9_xscom_ctrl_read() local
101 return val; in pnv_sbe_power9_xscom_ctrl_read()
131 sbe->host_doorbell = val; in pnv_sbe_set_host_doorbell()
134 qemu_set_irq(sbe->psi_irq, !!val); in pnv_sbe_set_host_doorbell()
246 val &= HOST_SBE_MSG_WAITING; in pnv_sbe_set_sbe_doorbell()
247 sbe->sbe_doorbell = val; in pnv_sbe_set_sbe_doorbell()
260 uint64_t val = 0; in pnv_sbe_power9_xscom_mbox_read() local
264 val = sbe->mbox[idx]; in pnv_sbe_power9_xscom_mbox_read()
268 val = sbe->sbe_doorbell; in pnv_sbe_power9_xscom_mbox_read()
281 return val; in pnv_sbe_power9_xscom_mbox_read()
[all …]
H A Dprep_systemio.c70 trace_prep_systemio_write(addr, val); in prep_port0092_write()
72 s->sreset = val & PORT0092_SOFTRESET; in prep_port0092_write()
75 if ((val & PORT0092_LE_MODE) != 0) { in prep_port0092_write()
99 trace_prep_systemio_write(addr, val); in prep_port0808_write()
107 trace_prep_systemio_write(addr, val); in prep_port0810_write()
133 uint32_t val = 0; in prep_port0818_read() local
134 trace_prep_systemio_read(addr, val); in prep_port0818_read()
135 return val; in prep_port0818_read()
172 s->system_control = val & mask; in prep_port081c_write()
234 uint32_t val = 0; in ppc_parity_error_readl() local
[all …]
/qemu/system/
H A Dmemory_ldst.c.inc28 uint64_t val;
67 return val;
97 uint64_t val;
136 return val;
164 uint64_t val;
182 val = ldub_p(ptr);
192 return val;
201 uint64_t val;
240 return val;
286 stl_p(ptr, val);
[all …]
/qemu/tests/unit/
H A Dtest-qga.c283 QDict *val; in test_qga_info() local
339 QDict *val; in test_qga_get_memory_block_info() local
793 QDict *val; in wait_for_guest_exec_completion() local
817 QDict *val; in test_qga_guest_exec() local
854 QDict *val; in test_qga_guest_exec_merged() local
877 QDict *val; in test_qga_guest_exec_separated() local
919 QDict *val; in test_qga_guest_exec_merged() local
990 QDict *val; in test_qga_guest_get_host_name() local
1004 QDict *val; in test_qga_guest_get_timezone() local
1019 QList *val; in test_qga_guest_get_users() local
[all …]
/qemu/fsdev/
H A D9p-iov-marshal.c89 copied = v9fs_unpack(&val, out_sg, out_num, offset, sizeof(val)); in v9fs_iov_vunmarshal()
93 *valp = val; in v9fs_iov_vunmarshal()
100 copied = v9fs_unpack(&val, out_sg, out_num, offset, sizeof(val)); in v9fs_iov_vunmarshal()
111 copied = v9fs_unpack(&val, out_sg, out_num, offset, sizeof(val)); in v9fs_iov_vunmarshal()
206 copied = v9fs_pack(in_sg, in_num, offset, &val, sizeof(val)); in v9fs_iov_vmarshal()
212 val = cpu_to_le16(val); in v9fs_iov_vmarshal()
214 copied = v9fs_pack(in_sg, in_num, offset, &val, sizeof(val)); in v9fs_iov_vmarshal()
220 val = cpu_to_le32(val); in v9fs_iov_vmarshal()
222 copied = v9fs_pack(in_sg, in_num, offset, &val, sizeof(val)); in v9fs_iov_vmarshal()
228 val = cpu_to_le64(val); in v9fs_iov_vmarshal()
[all …]
/qemu/hw/intc/
H A Dapic.c795 uint32_t val; in apic_register_read() local
820 val = s->tpr; in apic_register_read()
830 val = 0; in apic_register_read()
841 val = 0; in apic_register_read()
860 val = s->esr; in apic_register_read()
880 val = 0; in apic_register_read()
886 *value = val; in apic_register_read()
892 uint64_t val; in apic_mem_read() local
902 return val; in apic_mem_read()
966 s->tpr = val; in apic_register_write()
[all …]
H A Dloongarch_extioi.c117 uint32_t val; in extioi_enable_irq() local
120 val = mask & s->isr[index]; in extioi_enable_irq()
121 irq = ctz32(val); in extioi_enable_irq()
128 val &= ~(1 << irq); in extioi_enable_irq()
129 irq = ctz32(val); in extioi_enable_irq()
134 uint64_t val, bool notify) in extioi_update_sw_coremap() argument
142 val = cpu_to_le64(val); in extioi_update_sw_coremap()
145 cpu = val & 0xff; in extioi_update_sw_coremap()
146 val in extioi_update_sw_coremap()
168 extioi_update_sw_ipmap(LoongArchExtIOI * s,int index,uint64_t val) extioi_update_sw_ipmap() argument
188 extioi_writew(void * opaque,hwaddr addr,uint64_t val,unsigned size,MemTxAttrs attrs) extioi_writew() argument
[all...]
/qemu/target/microblaze/
H A Dgdbstub.c53 uint32_t val; in mb_cpu_gdb_read_register() local
60 val = env->pc; in mb_cpu_gdb_read_register()
66 val = env->ear; in mb_cpu_gdb_read_register()
69 val = env->esr; in mb_cpu_gdb_read_register()
72 val = env->fsr; in mb_cpu_gdb_read_register()
75 val = env->btr; in mb_cpu_gdb_read_register()
82 val = env->edr; in mb_cpu_gdb_read_register()
86 val = 0; in mb_cpu_gdb_read_register()
96 uint32_t val; in mb_cpu_gdb_read_stack_protect() local
100 val = env->slr; in mb_cpu_gdb_read_stack_protect()
[all …]
/qemu/tests/qtest/
H A Dtco-test.c86 uint32_t val; in stop_tco() local
89 val |= TCO_TMR_HLT; in stop_tco()
95 uint32_t val; in start_tco() local
121 uint32_t val; in reset_on_second_timeout() local
166 uint32_t val; in test_tco_timeout() local
210 uint32_t val; in test_tco_max_timeout() local
381 uint16_t val; in test_tco1_control_bits() local
387 val = TCO_LOCK; in test_tco1_control_bits()
389 val &= ~TCO_LOCK; in test_tco1_control_bits()
400 uint16_t val; in test_tco1_status_bits() local
[all …]
/qemu/include/block/
H A Dnvme.h121 #define NVME_CAP_SET_MQES(cap, val) \ argument
123 #define NVME_CAP_SET_CQR(cap, val) \ argument
125 #define NVME_CAP_SET_AMS(cap, val) \ argument
127 #define NVME_CAP_SET_TO(cap, val) \ argument
184 #define NVME_SET_CC_EN(cc, val) \ argument
186 #define NVME_SET_CC_CSS(cc, val) \ argument
188 #define NVME_SET_CC_MPS(cc, val) \ argument
190 #define NVME_SET_CC_AMS(cc, val) \ argument
192 #define NVME_SET_CC_SHN(cc, val) \ argument
194 #define NVME_SET_CC_IOSQES(cc, val) \ argument
[all …]

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