Home
last modified time | relevance | path

Searched refs:A32_BANKED_CURRENT_REG_SET (Results 1 – 18 of 18) sorted by relevance

/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dcpu.h1734 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ macro
H A Dhelper.c2387 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats_write()
2398 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats1h_write()
8281 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
8282 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
8291 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
8292 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dhelper.c3151 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats_write()
3162 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats1h_write()
8258 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
8259 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
8268 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
8269 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
H A Dcpu.h1994 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ macro
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dhelper.c3151 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats_write()
3162 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats1h_write()
8258 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
8259 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
8268 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
8269 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
H A Dcpu.h1994 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ macro
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dhelper.c3622 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats_write()
3638 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats1h_write()
9547 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9548 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
9557 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9558 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
H A Dcpu.h2133 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dhelper.c3666 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats_write()
3677 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats1h_write()
9387 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9388 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
9397 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9398 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
H A Dcpu.h2081 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dhelper.c3666 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats_write()
3677 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats1h_write()
9383 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9384 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
9393 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9394 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
H A Dcpu.h2081 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dhelper.c3626 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats_write()
3642 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats1h_write()
10031 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
10032 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
10041 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
10042 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
H A Dcpu.h2319 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ macro
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dhelper.c3402 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats_write()
3418 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats1h_write()
9769 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9770 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
9779 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9780 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
H A Dcpu.h2319 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ macro
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dhelper.c3656 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats_write()
3672 A32_BANKED_CURRENT_REG_SET(env, par, par64); in ats1h_write()
9683 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9684 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
9693 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); in arm_cpu_do_interrupt_aarch32()
9694 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); in arm_cpu_do_interrupt_aarch32()
H A Dcpu.h2282 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ macro