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Searched refs:AIPS2_OFF_BASE_ADDR (Results 1 – 25 of 127) sorted by relevance

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/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
[all …]
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h231 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) macro
249 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
250 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
252 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
254 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
256 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
259 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
260 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
261 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
262 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
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