| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 170 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
182 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
200 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
282 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 170 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
182 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
200 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
282 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 170 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
182 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
200 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
282 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 170 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
182 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
200 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
282 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | in ar934x_pll_init()
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); in ar934x_pll_init()
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_update_clock()
|