1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
4 */
5
6 #include <common.h>
7 #include <clock_legacy.h>
8 #include <command.h>
9 #include <hang.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/addrspace.h>
13 #include <asm/types.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <mach/ar71xx_regs.h>
17 #include <mach/ath79.h>
18 #include <wait_bit.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 /*
23 * The math for calculating PLL:
24 * NFRAC * 2^8
25 * NINT + -------------
26 * XTAL [MHz] 2^(18 - 1)
27 * PLL [MHz] = ------------ * ----------------------
28 * REFDIV 2^OUTDIV
29 *
30 * Unfortunatelly, there is no way to reliably compute the variables.
31 * The vendor U-Boot port contains macros for various combinations of
32 * CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern
33 * in those numbers.
34 */
35 struct ar934x_pll_config {
36 u8 range;
37 u8 refdiv;
38 u8 outdiv;
39 /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
40 u8 nint[2];
41 };
42
43 struct ar934x_clock_config {
44 u16 cpu_freq;
45 u16 ddr_freq;
46 u16 ahb_freq;
47
48 struct ar934x_pll_config cpu_pll;
49 struct ar934x_pll_config ddr_pll;
50 };
51
52 static const struct ar934x_clock_config ar934x_clock_config[] = {
53 { 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
54 { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
55 { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
56 { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
57 { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
58 { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
59 { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
60 { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
61 { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
62 { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
63 { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
64 { 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
65 { 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
66 { 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
67 { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
68 { 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
69 { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
70 { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
71 { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
72 { 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
73 { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
74 { 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
75 { 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
76 { 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
77 { 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
78 { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
79 { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
80 { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
81 };
82
ar934x_srif_pll_cfg(void __iomem * pll_reg_base,const u32 srif_val)83 static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val)
84 {
85 u32 reg;
86 do {
87 writel(0x10810f00, pll_reg_base + 0x4);
88 writel(srif_val, pll_reg_base + 0x0);
89 writel(0xd0810f00, pll_reg_base + 0x4);
90 writel(0x03000000, pll_reg_base + 0x8);
91 writel(0xd0800f00, pll_reg_base + 0x4);
92
93 clrbits_be32(pll_reg_base + 0x8, BIT(30));
94 udelay(5);
95 setbits_be32(pll_reg_base + 0x8, BIT(30));
96 udelay(5);
97
98 wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);
99
100 clrbits_be32(pll_reg_base + 0x8, BIT(30));
101 udelay(5);
102
103 /* Check if CPU SRIF PLL locked. */
104 reg = readl(pll_reg_base + 0x8);
105 reg = (reg & 0x7ffff8) >> 3;
106 } while (reg >= 0x40000);
107 }
108
ar934x_pll_init(const u16 cpu_mhz,const u16 ddr_mhz,const u16 ahb_mhz)109 void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
110 {
111 void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE,
112 AR934X_SRIF_SIZE, MAP_NOCACHE);
113 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
114 AR71XX_PLL_SIZE, MAP_NOCACHE);
115 const struct ar934x_pll_config *pll_cfg;
116 int i, pll_nint, pll_refdiv, xtal_40 = 0;
117 u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif;
118
119 /* Configure SRIF PLL with initial values. */
120 writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG);
121 writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG);
122 writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG);
123 writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG);
124 writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
125
126 /* Test for 40MHz XTAL */
127 reg = ath79_get_bootstrap();
128 if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
129 xtal_40 = 1;
130 cpu_srif = 0x41c00000;
131 ddr_srif = 0x41680000;
132 } else {
133 xtal_40 = 0;
134 cpu_srif = 0x29c00000;
135 ddr_srif = 0x29680000;
136 }
137
138 /* Locate CPU/DDR PLL configuration */
139 for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) {
140 if (cpu_mhz != ar934x_clock_config[i].cpu_freq)
141 continue;
142 if (ddr_mhz != ar934x_clock_config[i].ddr_freq)
143 continue;
144 if (ahb_mhz != ar934x_clock_config[i].ahb_freq)
145 continue;
146
147 /* Entry found */
148 pll_cfg = &ar934x_clock_config[i].cpu_pll;
149 pll_nint = pll_cfg->nint[xtal_40];
150 pll_refdiv = pll_cfg->refdiv;
151 cpu_pll =
152 (pll_nint << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) |
153 (pll_refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) |
154 (pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) |
155 (pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT);
156
157 pll_cfg = &ar934x_clock_config[i].ddr_pll;
158 pll_nint = pll_cfg->nint[xtal_40];
159 pll_refdiv = pll_cfg->refdiv;
160 ddr_pll =
161 (pll_nint << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) |
162 (pll_refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) |
163 (pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) |
164 (pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT);
165 break;
166 }
167
168 /* PLL configuration not found, hang. */
169 if (i == ARRAY_SIZE(ar934x_clock_config))
170 hang();
171
172 /* Set PLL Bypass */
173 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
174 AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
175 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
176 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
177 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
178 AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
179
180 /* Configure CPU PLL */
181 writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD,
182 pll_regs + AR934X_PLL_CPU_CONFIG_REG);
183 /* Configure DDR PLL */
184 writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD,
185 pll_regs + AR934X_PLL_DDR_CONFIG_REG);
186 /* Configure PLL routing */
187 writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS |
188 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS |
189 AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS |
190 (0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) |
191 (0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) |
192 (1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) |
193 AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL |
194 AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL |
195 AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL,
196 pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
197
198 /* Configure SRIF PLLs, which is completely undocumented :-) */
199 ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif);
200 ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif);
201
202 /* Unset PLL Bypass */
203 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
204 AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);
205 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
206 AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);
207 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
208 AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);
209
210 /* Enable PLL dithering */
211 writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) |
212 (0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT),
213 pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG);
214 writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT,
215 pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG);
216 }
217
ar934x_get_xtal(void)218 static u32 ar934x_get_xtal(void)
219 {
220 u32 val;
221
222 val = ath79_get_bootstrap();
223 if (val & AR934X_BOOTSTRAP_REF_CLK_40)
224 return 40000000;
225 else
226 return 25000000;
227 }
228
get_serial_clock(void)229 int get_serial_clock(void)
230 {
231 return ar934x_get_xtal();
232 }
233
ar934x_cpupll_to_hz(const u32 regval)234 static u32 ar934x_cpupll_to_hz(const u32 regval)
235 {
236 const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
237 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
238 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
239 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
240 const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
241 AR934X_PLL_CPU_CONFIG_NINT_MASK;
242 const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
243 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
244 const u32 xtal = ar934x_get_xtal();
245
246 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
247 }
248
ar934x_ddrpll_to_hz(const u32 regval)249 static u32 ar934x_ddrpll_to_hz(const u32 regval)
250 {
251 const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
252 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
253 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
254 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
255 const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
256 AR934X_PLL_DDR_CONFIG_NINT_MASK;
257 const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
258 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
259 const u32 xtal = ar934x_get_xtal();
260
261 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
262 }
263
ar934x_update_clock(void)264 static void ar934x_update_clock(void)
265 {
266 void __iomem *regs;
267 u32 ctrl, cpu, cpupll, ddr, ddrpll;
268 u32 cpudiv, ddrdiv, busdiv;
269 u32 cpuclk, ddrclk, busclk;
270
271 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
272 MAP_NOCACHE);
273
274 cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG);
275 ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG);
276 ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
277
278 cpupll = ar934x_cpupll_to_hz(cpu);
279 ddrpll = ar934x_ddrpll_to_hz(ddr);
280
281 if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
282 cpuclk = ar934x_get_xtal();
283 else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
284 cpuclk = cpupll;
285 else
286 cpuclk = ddrpll;
287
288 if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
289 ddrclk = ar934x_get_xtal();
290 else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
291 ddrclk = ddrpll;
292 else
293 ddrclk = cpupll;
294
295 if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
296 busclk = ar934x_get_xtal();
297 else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
298 busclk = ddrpll;
299 else
300 busclk = cpupll;
301
302 cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
303 AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
304 ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
305 AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
306 busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
307 AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
308
309 gd->cpu_clk = cpuclk / (cpudiv + 1);
310 gd->mem_clk = ddrclk / (ddrdiv + 1);
311 gd->bus_clk = busclk / (busdiv + 1);
312 }
313
get_bus_freq(ulong dummy)314 ulong get_bus_freq(ulong dummy)
315 {
316 ar934x_update_clock();
317 return gd->bus_clk;
318 }
319
get_ddr_freq(ulong dummy)320 ulong get_ddr_freq(ulong dummy)
321 {
322 ar934x_update_clock();
323 return gd->mem_clk;
324 }
325
do_ar934x_showclk(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])326 int do_ar934x_showclk(struct cmd_tbl *cmdtp, int flag, int argc,
327 char *const argv[])
328 {
329 ar934x_update_clock();
330 printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000);
331 printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000);
332 printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000);
333 return 0;
334 }
335
336 U_BOOT_CMD(
337 clocks, CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk,
338 "display clocks",
339 ""
340 );
341