/dports/emulators/qemu42/qemu-4.2.1/hw/intc/ |
H A D | armv7m_nvic.c | 94 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { in nvic_rettobase() 501 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_clear_pending() 540 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in do_armv7m_nvic_set_pending() 687 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_set_pending_lazyfp() 771 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_acknowledge_irq() 801 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_get_pending_irq_info() 822 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_complete_irq() 911 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_get_ready_status() 2435 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load() 2554 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; in armv7m_nvic_reset()
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/dports/emulators/qemu/qemu-6.2.0/hw/intc/ |
H A D | armv7m_nvic.c | 108 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { in nvic_rettobase() 514 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_clear_pending() 553 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in do_armv7m_nvic_set_pending() 700 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_set_pending_lazyfp() 784 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_acknowledge_irq() 824 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_get_pending_irq_info() 840 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_complete_irq() 934 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_get_ready_status() 2482 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load() 2601 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; in armv7m_nvic_reset()
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/dports/emulators/qemu5/qemu-5.2.0/hw/intc/ |
H A D | armv7m_nvic.c | 109 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { in nvic_rettobase() 516 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_clear_pending() 555 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in do_armv7m_nvic_set_pending() 702 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_set_pending_lazyfp() 786 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_acknowledge_irq() 816 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_get_pending_irq_info() 837 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_complete_irq() 926 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_get_ready_status() 2491 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load() 2610 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; in armv7m_nvic_reset()
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/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/ |
H A D | armv7m_nvic.c | 94 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { in nvic_rettobase() 501 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_clear_pending() 540 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in do_armv7m_nvic_set_pending() 687 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_set_pending_lazyfp() 771 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_acknowledge_irq() 801 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_get_pending_irq_info() 822 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_complete_irq() 911 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_get_ready_status() 2435 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load() 2554 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; in armv7m_nvic_reset()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/ |
H A D | armv7m_nvic.c | 94 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { 501 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 540 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 687 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 771 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); 801 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); 822 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 911 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); 2435 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || 2554 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/ |
H A D | armv7m_nvic.c | 94 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { in nvic_rettobase() 501 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_clear_pending() 540 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in do_armv7m_nvic_set_pending() 687 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_set_pending_lazyfp() 771 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_acknowledge_irq() 801 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_get_pending_irq_info() 822 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_complete_irq() 911 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_get_ready_status() 2435 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load() 2554 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; in armv7m_nvic_reset()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/ |
H A D | armv7m_nvic.c | 108 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { in nvic_rettobase() 514 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_clear_pending() 553 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in do_armv7m_nvic_set_pending() 700 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_set_pending_lazyfp() 784 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_acknowledge_irq() 824 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_get_pending_irq_info() 840 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_complete_irq() 934 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_get_ready_status() 2482 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load() 2601 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; in armv7m_nvic_reset()
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/dports/emulators/qemu60/qemu-6.0.0/hw/intc/ |
H A D | armv7m_nvic.c | 109 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { in nvic_rettobase() 516 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_clear_pending() 555 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in do_armv7m_nvic_set_pending() 702 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_set_pending_lazyfp() 786 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_acknowledge_irq() 816 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_get_pending_irq_info() 837 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_complete_irq() 931 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_get_ready_status() 2633 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load() 2752 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; in armv7m_nvic_reset()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/ |
H A D | armv7m_nvic.c | 91 for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) { in nvic_rettobase() 493 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_clear_pending() 532 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in do_armv7m_nvic_set_pending() 667 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_acknowledge_irq() 697 assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); in armv7m_nvic_get_pending_irq_info() 718 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); in armv7m_nvic_complete_irq() 2095 if (s->vectors[ARMV7M_EXCP_RESET].prio != resetprio || in nvic_post_load() 2212 s->vectors[ARMV7M_EXCP_RESET].prio = resetprio; in armv7m_nvic_reset()
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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/ |
H A D | cpu.h | 45 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu.h | 60 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu.h | 60 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
H A D | cpu.h | 62 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
H A D | cpu.h | 54 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
H A D | cpu.h | 54 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
H A D | cpu.h | 59 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
H A D | cpu.h | 54 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
H A D | cpu.h | 54 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
H A D | cpu.h | 59 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
H A D | cpu.h | 60 #define ARMV7M_EXCP_RESET 1 macro
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/dports/emulators/qemu/qemu-6.2.0/target/arm/ |
H A D | cpu.h | 60 #define ARMV7M_EXCP_RESET 1 macro
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