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Searched refs:ARMV7M_EXCP_SVC (Results 1 – 25 of 31) sorted by relevance

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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A Darmv7m_nvic.c139 exc == ARMV7M_EXCP_SVC || in exc_is_banked()
919 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
934 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
972 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
987 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1379 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1404 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1409 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
1744 case ARMV7M_EXCP_SVC: in shpr_bank()
2206 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A Darmv7m_nvic.c142 exc == ARMV7M_EXCP_SVC || in exc_is_banked()
1099 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1114 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1152 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1167 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1616 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1641 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1646 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
2063 case ARMV7M_EXCP_SVC: in shpr_bank()
2546 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Darmv7m_nvic.c155 exc == ARMV7M_EXCP_SVC || in exc_is_banked()
1146 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1161 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1199 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1214 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1729 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1754 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1759 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
2189 case ARMV7M_EXCP_SVC: in shpr_bank()
2593 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A Darmv7m_nvic.c157 exc == ARMV7M_EXCP_SVC || in exc_is_banked()
1114 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1129 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1167 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1182 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1672 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1697 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1702 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
2119 case ARMV7M_EXCP_SVC: in shpr_bank()
2602 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A Darmv7m_nvic.c142 exc == ARMV7M_EXCP_SVC || in exc_is_banked()
1099 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1114 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1152 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1167 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1616 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1641 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1646 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
2063 case ARMV7M_EXCP_SVC: in shpr_bank()
2546 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A Darmv7m_nvic.c142 exc == ARMV7M_EXCP_SVC ||
1099 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) {
1114 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) {
1152 if (s->vectors[ARMV7M_EXCP_SVC].active) {
1167 if (s->vectors[ARMV7M_EXCP_SVC].pending) {
1616 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
1641 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0;
1646 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0;
2063 case ARMV7M_EXCP_SVC:
2546 s->vectors[ARMV7M_EXCP_SVC].enabled = 1;
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/
H A Darmv7m_nvic.c142 exc == ARMV7M_EXCP_SVC || in exc_is_banked()
1099 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1114 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1152 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1167 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1616 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1641 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1646 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
2063 case ARMV7M_EXCP_SVC: in shpr_bank()
2546 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A Darmv7m_nvic.c155 exc == ARMV7M_EXCP_SVC || in exc_is_banked()
1146 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1161 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1199 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1214 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1729 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1754 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1759 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
2189 case ARMV7M_EXCP_SVC: in shpr_bank()
2593 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Darmv7m_nvic.c157 exc == ARMV7M_EXCP_SVC || in exc_is_banked()
1131 if (s->sec_vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1146 if (s->sec_vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1184 if (s->vectors[ARMV7M_EXCP_SVC].active) { in nvic_readl()
1199 if (s->vectors[ARMV7M_EXCP_SVC].pending) { in nvic_readl()
1714 s->sec_vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1739 s->vectors[ARMV7M_EXCP_SVC].active = (value & (1 << 7)) != 0; in nvic_writel()
1744 s->vectors[ARMV7M_EXCP_SVC].pending = (value & (1 << 15)) != 0; in nvic_writel()
2174 case ARMV7M_EXCP_SVC: in shpr_bank()
2744 s->vectors[ARMV7M_EXCP_SVC].enabled = 1; in armv7m_nvic_reset()
[all …]
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/
H A Dcpu.h51 #define ARMV7M_EXCP_SVC 11 macro
H A Dhelper.c679 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC); in do_interrupt_v7m()
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dcpu.h66 #define ARMV7M_EXCP_SVC 11 macro
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dcpu.h66 #define ARMV7M_EXCP_SVC 11 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dcpu.h69 #define ARMV7M_EXCP_SVC 11 macro
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dm_helper.c2092 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
H A Dcpu.h61 #define ARMV7M_EXCP_SVC 11 macro
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dm_helper.c2096 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
H A Dcpu.h66 #define ARMV7M_EXCP_SVC 11 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dm_helper.c2093 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
H A Dcpu.h61 #define ARMV7M_EXCP_SVC 11 macro
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dm_helper.c2092 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
H A Dcpu.h61 #define ARMV7M_EXCP_SVC 11 macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dm_helper.c2093 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dm_helper.c2215 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); in arm_v7m_cpu_do_interrupt()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dm_helper.c2261 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); in arm_v7m_cpu_do_interrupt()

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