/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
H A D | helper.c | 771 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 787 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 2712 .secure = ARM_CP_SECSTATE_NS, 2753 .secure = ARM_CP_SECSTATE_NS, 2805 .secure = ARM_CP_SECSTATE_NS, 7094 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable() 7336 case ARM_CP_SECSTATE_NS: in define_one_arm_cp_reg_with_opaque() 7348 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque() 7356 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque()
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H A D | cpu.h | 2296 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ enumerator
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/dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
H A D | helper.c | 771 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 787 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 2712 .secure = ARM_CP_SECSTATE_NS, 2753 .secure = ARM_CP_SECSTATE_NS, 2805 .secure = ARM_CP_SECSTATE_NS, 7094 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable() 7336 case ARM_CP_SECSTATE_NS: in define_one_arm_cp_reg_with_opaque() 7348 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque() 7356 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque()
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H A D | cpu.h | 2296 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ enumerator
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/dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
H A D | helper.c | 862 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 879 .secure = ARM_CP_SECSTATE_NS, 3154 .secure = ARM_CP_SECSTATE_NS, 3199 .secure = ARM_CP_SECSTATE_NS, 3251 .secure = ARM_CP_SECSTATE_NS, 8325 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable() 8593 case ARM_CP_SECSTATE_NS: in define_one_arm_cp_reg_with_opaque() 8605 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque() 8613 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque()
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H A D | cpu.h | 2437 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ enumerator
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
H A D | helper.c | 913 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 930 .secure = ARM_CP_SECSTATE_NS, 3201 .secure = ARM_CP_SECSTATE_NS, 3246 .secure = ARM_CP_SECSTATE_NS, 3298 .secure = ARM_CP_SECSTATE_NS, 8194 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable() 8433 case ARM_CP_SECSTATE_NS: in define_one_arm_cp_reg_with_opaque() 8445 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque() 8453 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque()
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H A D | cpu.h | 2383 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ enumerator
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
H A D | helper.c | 726 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 742 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 2019 .secure = ARM_CP_SECSTATE_NS, 2060 .secure = ARM_CP_SECSTATE_NS, 2112 .secure = ARM_CP_SECSTATE_NS, 5748 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable() 5986 case ARM_CP_SECSTATE_NS: in define_one_arm_cp_reg_with_opaque() 5998 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque() 6006 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque()
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H A D | cpu.h | 2002 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ enumerator
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
H A D | helper.c | 913 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 930 .secure = ARM_CP_SECSTATE_NS, 3201 .secure = ARM_CP_SECSTATE_NS, 3246 .secure = ARM_CP_SECSTATE_NS, 3298 .secure = ARM_CP_SECSTATE_NS, 8193 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable() 8432 case ARM_CP_SECSTATE_NS: in define_one_arm_cp_reg_with_opaque() 8444 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque() 8452 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque()
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H A D | cpu.h | 2383 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ enumerator
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
H A D | helper.c | 872 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 889 .secure = ARM_CP_SECSTATE_NS, 3151 .secure = ARM_CP_SECSTATE_NS, 3196 .secure = ARM_CP_SECSTATE_NS, 3248 .secure = ARM_CP_SECSTATE_NS, 8779 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable() 9047 case ARM_CP_SECSTATE_NS: in define_one_arm_cp_reg_with_opaque() 9059 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque() 9067 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque()
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H A D | cpu.h | 2623 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ enumerator
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/dports/emulators/qemu/qemu-6.2.0/target/arm/ |
H A D | helper.c | 648 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 665 .secure = ARM_CP_SECSTATE_NS, 2927 .secure = ARM_CP_SECSTATE_NS, 2972 .secure = ARM_CP_SECSTATE_NS, 3024 .secure = ARM_CP_SECSTATE_NS, 8517 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable() 8785 case ARM_CP_SECSTATE_NS: in define_one_arm_cp_reg_with_opaque() 8797 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque() 8805 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque()
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H A D | cpu.h | 2623 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ enumerator
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/dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
H A D | helper.c | 872 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, 889 .secure = ARM_CP_SECSTATE_NS, 3181 .secure = ARM_CP_SECSTATE_NS, 3226 .secure = ARM_CP_SECSTATE_NS, 3278 .secure = ARM_CP_SECSTATE_NS, 8454 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable() 8722 case ARM_CP_SECSTATE_NS: in define_one_arm_cp_reg_with_opaque() 8734 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque() 8742 ARM_CP_SECSTATE_NS, in define_one_arm_cp_reg_with_opaque()
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H A D | cpu.h | 2586 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ enumerator
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