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Searched refs:ARM_CP_STATE_AA32 (Results 1 – 25 of 40) sorted by relevance

12

/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dgdbstub.c137 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_xml()
H A Dhelper.c2153 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2158 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
4603 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
4666 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
4823 { .name = "HCR", .state = ARM_CP_STATE_AA32,
4898 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5067 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5219 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
7110 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
7263 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dgdbstub.c138 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_xml()
H A Dhelper.c1478 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1483 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
3802 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3865 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
3925 { .name = "HCR", .state = ARM_CP_STATE_AA32,
3996 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
4165 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
4317 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
5764 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
5917 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dgdbstub.c137 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_xml()
H A Dhelper.c2153 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2158 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
4603 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
4666 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
4823 { .name = "HCR", .state = ARM_CP_STATE_AA32,
4898 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5067 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5219 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
7110 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
7263 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dhelper.c2332 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2338 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
5246 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5447 { .name = "HCR", .state = ARM_CP_STATE_AA32,
5520 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5689 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
6017 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
8341 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
8503 case ARM_CP_STATE_AA32: in define_one_arm_cp_reg_with_opaque()
8523 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
H A Dgdbstub.c153 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_xml()
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dgdbstub.c153 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_xml()
H A Dhelper.c2356 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2362 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
5338 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5539 { .name = "HCR", .state = ARM_CP_STATE_AA32,
5612 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5779 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
6131 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
8470 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
8632 case ARM_CP_STATE_AA32: in define_one_arm_cp_reg_with_opaque()
8652 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dgdbstub.c139 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_xml()
H A Dhelper.c2379 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2385 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
5224 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5287 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5483 { .name = "HCR", .state = ARM_CP_STATE_AA32,
5556 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5725 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
6050 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
8210 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
8363 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dgdbstub.c157 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_xml()
H A Dhelper.c2312 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2318 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
5477 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5678 { .name = "HCR", .state = ARM_CP_STATE_AA32,
5751 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5918 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
6270 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
8795 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
8957 case ARM_CP_STATE_AA32: in define_one_arm_cp_reg_with_opaque()
8977 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dgdbstub.c140 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_xml()
H A Dhelper.c2379 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2385 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
5224 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5287 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5483 { .name = "HCR", .state = ARM_CP_STATE_AA32,
5556 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5725 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
6050 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
8209 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
8362 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dhelper.c2088 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
2094 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
5253 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5454 { .name = "HCR", .state = ARM_CP_STATE_AA32,
5527 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5694 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
6046 if (ri->state == ARM_CP_STATE_AA32) { in oslar_write()
8533 if (state == ARM_CP_STATE_AA32) { in add_cpreg_to_hashtable()
8695 case ARM_CP_STATE_AA32: in define_one_arm_cp_reg_with_opaque()
8715 if (r->state != ARM_CP_STATE_AA32) { in define_one_arm_cp_reg_with_opaque()
[all …]
H A Dgdbstub.c285 if (ri->state == ARM_CP_STATE_AA32) { in arm_register_sysreg_for_xml()
/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A Darm_gicv3_cpuif.c2387 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2414 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2654 { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, in gicv3_init_cpuif()
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Darm_gicv3_cpuif.c2414 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2441 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2679 { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, in gicv3_init_cpuif()
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Darm_gicv3_cpuif.c2391 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2418 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2656 { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, in gicv3_init_cpuif()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A Darm_gicv3_cpuif.c2387 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2414 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2654 { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, in gicv3_init_cpuif()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A Darm_gicv3_cpuif.c2385 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2412 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2652 { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, in gicv3_init_cpuif()
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A Darm_gicv3_cpuif.c2391 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2418 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2656 { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, in gicv3_init_cpuif()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A Darm_gicv3_cpuif.c2390 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2417 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2657 { .name = "ICH_LRCn_EL2", .state = ARM_CP_STATE_AA32, in gicv3_init_cpuif()

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