| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/ |
| H A D | PmcRegs.h | 45 #define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
63 #define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
67 #define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
68 #define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
102 #define B_ACPI_IO_SMI_STS_MCSMI BIT11
138 #define B_ACPI_IO_GPE0_STS_127_96_PME BIT11
152 #define B_ACPI_IO_GPE0_EN_127_96_PME BIT11
242 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8)
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/ |
| H A D | PchRegsPmc.h | 57 #define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
86 #define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
90 #define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
91 #define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
108 #define B_ACPI_IO_SMI_EN_MCSMI BIT11
149 #define B_ACPI_IO_SMI_STS_MCSMI BIT11
229 #define B_ACPI_IO_GPE0_STS_127_96_PME BIT11
257 #define B_ACPI_IO_GPE0_EN_127_96_PME BIT11
309 #define B_TCO_IO_TCO1_CNT_TMR_HLT BIT11
440 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C3 BIT11
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| H A D | PchRegsHsio.h | 45 #define B_HSIO_PCR_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9)
93 #define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 |…
135 #define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
141 #define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
150 #define B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
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| H A D | PchRegsFia.h | 61 #define B_PCH_FIA_PCR_L2O (BIT11 | BIT10 | BIT9 | BIT8)
69 #define B_PCH_FIA_PCR_L10O (BIT11 | BIT10 | BIT9 | BIT8)
77 #define B_PCH_FIA_PCR_L18O (BIT11 | BIT10 | BIT9 | BIT8)
85 #define B_PCH_FIA_PCR_L26O (BIT11 | BIT10 | BIT9 | BIT8)
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| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 75 #define TCR_FDUPLX BIT11
94 #define EPHSR_EXC_DEF BIT11
118 #define RPCR_ANEG BIT11
137 #define CTR_AUTO_REL BIT11
171 #define PTR_NOT_EMPTY BIT11
200 #define RX_TOO_LONG BIT11
242 #define PHYCR_PD BIT11 // Power-Down switch
255 #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 75 #define TCR_FDUPLX BIT11
94 #define EPHSR_EXC_DEF BIT11
118 #define RPCR_ANEG BIT11
137 #define CTR_AUTO_REL BIT11
171 #define PTR_NOT_EMPTY BIT11
200 #define RX_TOO_LONG BIT11
242 #define PHYCR_PD BIT11 // Power-Down switch
255 #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability
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| /dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/EmbeddedPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 75 #define TCR_FDUPLX BIT11
94 #define EPHSR_EXC_DEF BIT11
118 #define RPCR_ANEG BIT11
137 #define CTR_AUTO_REL BIT11
171 #define PTR_NOT_EMPTY BIT11
200 #define RX_TOO_LONG BIT11
242 #define PHYCR_PD BIT11 // Power-Down switch
255 #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/EmbeddedPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 75 #define TCR_FDUPLX BIT11
94 #define EPHSR_EXC_DEF BIT11
118 #define RPCR_ANEG BIT11
137 #define CTR_AUTO_REL BIT11
171 #define PTR_NOT_EMPTY BIT11
200 #define RX_TOO_LONG BIT11
242 #define PHYCR_PD BIT11 // Power-Down switch
255 #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/ARM/VExpressPkg/Drivers/Lan91xDxe/ |
| H A D | Lan91xDxeHw.h | 82 #define TCR_FDUPLX BIT11
101 #define EPHSR_EXC_DEF BIT11
125 #define RPCR_ANEG BIT11
144 #define CTR_AUTO_REL BIT11
178 #define PTR_NOT_EMPTY BIT11
207 #define RX_TOO_LONG BIT11
249 #define PHYCR_PD BIT11 // Power-Down switch
262 #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/ |
| H A D | PchRegsPmc.h | 114 #define B_PCH_PMC_BM_CX_CNF_MASK_CF BIT11
131 #define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11
162 #define B_PCH_ACPI_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
166 #define V_PCH_ACPI_PM1_CNT_S4 (BIT12 | BIT11)
167 #define V_PCH_ACPI_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
184 #define B_PCH_SMI_EN_MCSMI BIT11
225 #define B_PCH_SMI_STS_MCSMI BIT11
303 #define B_PCH_ACPI_GPE0_STS_127_96_PME BIT11
330 #define B_PCH_ACPI_GPE0_EN_127_96_PME BIT11
384 #define B_PCH_TCO_CNT_TMR_HLT BIT11
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| H A D | PchRegsHsio.h | 15 #define B_PCH_HSIO_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9)
69 #define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 |…
111 #define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
117 #define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
126 #define B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT…
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/ |
| H A D | PchRegsPmc.h | 115 #define B_PCH_PMC_BM_CX_CNF_MASK_CF BIT11
132 #define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11
163 #define B_PCH_ACPI_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
167 #define V_PCH_ACPI_PM1_CNT_S4 (BIT12 | BIT11)
168 #define V_PCH_ACPI_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
185 #define B_PCH_SMI_EN_MCSMI BIT11
226 #define B_PCH_SMI_STS_MCSMI BIT11
304 #define B_PCH_ACPI_GPE0_STS_127_96_PME BIT11
331 #define B_PCH_ACPI_GPE0_EN_127_96_PME BIT11
385 #define B_PCH_TCO_CNT_TMR_HLT BIT11
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Include/ |
| H A D | PcieRegs.h | 74 #define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptabl…
103 #define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Active State Power Managemen…
105 #define B_PCIE_LCAP_APMS_L1 BIT11
126 #define B_PCIE_LSTS_LT BIT11 ///< Link Training
167 #define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism Supported
203 #define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) ///< PME …
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Include/ |
| H A D | PcieRegs.h | 75 #define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptabl…
104 #define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Active State Power Managemen…
106 #define B_PCIE_LCAP_APMS_L1 BIT11
127 #define B_PCIE_LSTS_LT BIT11 ///< Link Training
168 #define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism Supported
204 #define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) ///< PME …
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| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/ |
| H A D | PcieRegs.h | 42 #define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptabl…
59 #define B_PCIE_LCAP_APMS_L1 BIT11
76 #define B_PCIE_LSTS_LT BIT11 ///< Link Training
88 #define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism Supported
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| /dports/emulators/qemu60/qemu-6.0.0/roms/edk2/IntelFsp2Pkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 27 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
28 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
44 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/IntelFspPkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 27 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
28 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
44 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/IntelFsp2Pkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 27 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
28 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
44 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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| /dports/emulators/qemu/qemu-6.2.0/roms/edk2/IntelFsp2Pkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 27 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
28 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
44 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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| /dports/emulators/qemu5/qemu-5.2.0/roms/edk2/IntelFsp2Pkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 27 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
28 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
44 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/IntelFsp2Pkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 27 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
28 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
44 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/IntelFspPkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 27 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
28 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
44 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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| /dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/IntelFsp2Pkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 27 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
28 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
44 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/IntelFspPkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 33 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
34 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
50 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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| /dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/IntelFsp2Pkg/Library/BaseCacheLib/ |
| H A D | CacheLibInternal.h | 27 #define B_EFI_MSR_CACHE_MTRR_VALID BIT11
28 #define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
44 #define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
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