/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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H A D | brw_fs_nir.cpp | 643 retype(temp, BRW_REGISTER_TYPE_UD)); in emit_find_msb_using_lzd() 874 op[0].type = BRW_REGISTER_TYPE_UD; in emit_fsign() 875 result.type = BRW_REGISTER_TYPE_UD; in emit_fsign() 2209 vertex_count.type = BRW_REGISTER_TYPE_UD; in emit_gs_end_primitive() 2410 vertex_count.type = BRW_REGISTER_TYPE_UD; in emit_gs_vertex() 2533 BRW_REGISTER_TYPE_UD); in emit_gs_input_load() 2723 BRW_REGISTER_TYPE_UD)); in get_tcs_single_patch_icp_handle() 3449 dest.type = BRW_REGISTER_TYPE_UD; in nir_emit_fs_intrinsic() 3459 dest.type = BRW_REGISTER_TYPE_UD; in nir_emit_fs_intrinsic() 5364 flag.type = BRW_REGISTER_TYPE_UD; in nir_emit_intrinsic() [all …]
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/dports/lang/clover/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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H A D | brw_fs_nir.cpp | 643 retype(temp, BRW_REGISTER_TYPE_UD)); in emit_find_msb_using_lzd() 874 op[0].type = BRW_REGISTER_TYPE_UD; in emit_fsign() 875 result.type = BRW_REGISTER_TYPE_UD; in emit_fsign() 2209 vertex_count.type = BRW_REGISTER_TYPE_UD; in emit_gs_end_primitive() 2410 vertex_count.type = BRW_REGISTER_TYPE_UD; in emit_gs_vertex() 2533 BRW_REGISTER_TYPE_UD); in emit_gs_input_load() 2723 BRW_REGISTER_TYPE_UD)); in get_tcs_single_patch_icp_handle() 3449 dest.type = BRW_REGISTER_TYPE_UD; in nir_emit_fs_intrinsic() 3459 dest.type = BRW_REGISTER_TYPE_UD; in nir_emit_fs_intrinsic() 5364 flag.type = BRW_REGISTER_TYPE_UD; in nir_emit_intrinsic() [all …]
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/dports/graphics/libosmesa/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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H A D | brw_fs_nir.cpp | 643 retype(temp, BRW_REGISTER_TYPE_UD)); in emit_find_msb_using_lzd() 874 op[0].type = BRW_REGISTER_TYPE_UD; in emit_fsign() 875 result.type = BRW_REGISTER_TYPE_UD; in emit_fsign() 2209 vertex_count.type = BRW_REGISTER_TYPE_UD; in emit_gs_end_primitive() 2410 vertex_count.type = BRW_REGISTER_TYPE_UD; in emit_gs_vertex() 2533 BRW_REGISTER_TYPE_UD); in emit_gs_input_load() 2723 BRW_REGISTER_TYPE_UD)); in get_tcs_single_patch_icp_handle() 3449 dest.type = BRW_REGISTER_TYPE_UD; in nir_emit_fs_intrinsic() 3459 dest.type = BRW_REGISTER_TYPE_UD; in nir_emit_fs_intrinsic() 5364 flag.type = BRW_REGISTER_TYPE_UD; in nir_emit_intrinsic() [all …]
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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/dports/graphics/mesa-libs/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_fs_nir.cpp | 656 bld.LZD(retype(result, BRW_REGISTER_TYPE_UD), in emit_find_msb_using_lzd() 657 retype(temp, BRW_REGISTER_TYPE_UD)); in emit_find_msb_using_lzd() 888 op[0].type = BRW_REGISTER_TYPE_UD; in emit_fsign() 889 result.type = BRW_REGISTER_TYPE_UD; in emit_fsign() 2211 vertex_count.type = BRW_REGISTER_TYPE_UD; in emit_gs_end_primitive() 2412 vertex_count.type = BRW_REGISTER_TYPE_UD; in emit_gs_vertex() 2535 BRW_REGISTER_TYPE_UD); in emit_gs_input_load() 2725 BRW_REGISTER_TYPE_UD)); in get_tcs_single_patch_icp_handle() 3457 dest.type = BRW_REGISTER_TYPE_UD; in nir_emit_fs_intrinsic() 5384 flag.type = BRW_REGISTER_TYPE_UD; in nir_emit_intrinsic() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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/dports/graphics/mesa-dri/mesa-21.3.6/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 250 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 257 [BRW_REGISTER_TYPE_UD] = { GFX7_3SRC_TYPE_UD }, 269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 294 [BRW_REGISTER_TYPE_UD] = { GFX12_HW_REG_TYPE_UINT(2), E(INT), }, 517 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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H A D | brw_reg_type.h | 59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */ enumerator 92 case BRW_REGISTER_TYPE_UD: in brw_reg_type_is_integer() 108 tp == BRW_REGISTER_TYPE_UD || in brw_reg_type_is_unsigned_integer() 152 case BRW_REGISTER_TYPE_UD: in brw_reg_type_from_bit_size() 160 return BRW_REGISTER_TYPE_UD; in brw_reg_type_from_bit_size()
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/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/compiler/ |
H A D | brw_reg_type.c | 101 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 114 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 129 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 147 [BRW_REGISTER_TYPE_UD] = { BRW_HW_REG_TYPE_UD, BRW_HW_IMM_TYPE_UD }, 232 [BRW_REGISTER_TYPE_UD] = { GEN7_3SRC_TYPE_UD }, 239 [BRW_REGISTER_TYPE_UD] = { GEN7_3SRC_TYPE_UD }, 251 [BRW_REGISTER_TYPE_UD] = { GEN10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 264 [BRW_REGISTER_TYPE_UD] = { GEN10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) }, 276 [BRW_REGISTER_TYPE_UD] = { GEN12_HW_REG_TYPE_UINT(2), E(INT), }, 474 [BRW_REGISTER_TYPE_UD] = 4, in brw_reg_type_to_size() [all …]
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