1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef BRW_REG_TYPE_H
25 #define BRW_REG_TYPE_H
26
27 #include <stdbool.h>
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #ifdef HAVE_FUNC_ATTRIBUTE_PURE
34 #define ATTRIBUTE_PURE __attribute__((__pure__))
35 #else
36 #define ATTRIBUTE_PURE
37 #endif
38
39 enum brw_reg_file;
40 struct intel_device_info;
41
42 /*
43 * The ordering has been chosen so that no enum value is the same as a
44 * compatible hardware encoding.
45 */
46 enum PACKED brw_reg_type {
47 /** Floating-point types: @{ */
48 BRW_REGISTER_TYPE_NF, /* >64-bit (accumulator-only) native float (gfx11+) */
49 BRW_REGISTER_TYPE_DF, /* 64-bit float (double float) */
50 BRW_REGISTER_TYPE_F, /* 32-bit float */
51 BRW_REGISTER_TYPE_HF, /* 16-bit float (half float) */
52 BRW_REGISTER_TYPE_VF, /* 32-bit vector of 4 8-bit floats */
53 /** @} */
54
55 /** Integer types: @{ */
56 BRW_REGISTER_TYPE_Q, /* 64-bit signed integer (quad word) */
57 BRW_REGISTER_TYPE_UQ, /* 64-bit unsigned integer (quad word) */
58 BRW_REGISTER_TYPE_D, /* 32-bit signed integer (double word) */
59 BRW_REGISTER_TYPE_UD, /* 32-bit unsigned integer (double word) */
60 BRW_REGISTER_TYPE_W, /* 16-bit signed integer (word) */
61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */
62 BRW_REGISTER_TYPE_B, /* 8-bit signed integer (byte) */
63 BRW_REGISTER_TYPE_UB, /* 8-bit unsigned integer (byte) */
64 BRW_REGISTER_TYPE_V, /* vector of 8 signed 4-bit integers (treated as W) */
65 BRW_REGISTER_TYPE_UV, /* vector of 8 unsigned 4-bit integers (treated as UW) */
66 /** @} */
67
68 BRW_REGISTER_TYPE_LAST = BRW_REGISTER_TYPE_UV
69 };
70
71 static inline bool
brw_reg_type_is_floating_point(enum brw_reg_type type)72 brw_reg_type_is_floating_point(enum brw_reg_type type)
73 {
74 switch (type) {
75 case BRW_REGISTER_TYPE_NF:
76 case BRW_REGISTER_TYPE_DF:
77 case BRW_REGISTER_TYPE_F:
78 case BRW_REGISTER_TYPE_HF:
79 return true;
80 default:
81 return false;
82 }
83 }
84
85 static inline bool
brw_reg_type_is_integer(enum brw_reg_type type)86 brw_reg_type_is_integer(enum brw_reg_type type)
87 {
88 switch (type) {
89 case BRW_REGISTER_TYPE_Q:
90 case BRW_REGISTER_TYPE_UQ:
91 case BRW_REGISTER_TYPE_D:
92 case BRW_REGISTER_TYPE_UD:
93 case BRW_REGISTER_TYPE_W:
94 case BRW_REGISTER_TYPE_UW:
95 case BRW_REGISTER_TYPE_B:
96 case BRW_REGISTER_TYPE_UB:
97 return true;
98 default:
99 return false;
100 }
101 }
102
103 static inline bool
brw_reg_type_is_unsigned_integer(enum brw_reg_type tp)104 brw_reg_type_is_unsigned_integer(enum brw_reg_type tp)
105 {
106 return tp == BRW_REGISTER_TYPE_UB ||
107 tp == BRW_REGISTER_TYPE_UW ||
108 tp == BRW_REGISTER_TYPE_UD ||
109 tp == BRW_REGISTER_TYPE_UQ;
110 }
111
112 /*
113 * Returns a type based on a reference_type (word, float, half-float) and a
114 * given bit_size.
115 */
116 static inline enum brw_reg_type
brw_reg_type_from_bit_size(unsigned bit_size,enum brw_reg_type reference_type)117 brw_reg_type_from_bit_size(unsigned bit_size,
118 enum brw_reg_type reference_type)
119 {
120 switch(reference_type) {
121 case BRW_REGISTER_TYPE_HF:
122 case BRW_REGISTER_TYPE_F:
123 case BRW_REGISTER_TYPE_DF:
124 switch(bit_size) {
125 case 16:
126 return BRW_REGISTER_TYPE_HF;
127 case 32:
128 return BRW_REGISTER_TYPE_F;
129 case 64:
130 return BRW_REGISTER_TYPE_DF;
131 default:
132 unreachable("Invalid bit size");
133 }
134 case BRW_REGISTER_TYPE_B:
135 case BRW_REGISTER_TYPE_W:
136 case BRW_REGISTER_TYPE_D:
137 case BRW_REGISTER_TYPE_Q:
138 switch(bit_size) {
139 case 8:
140 return BRW_REGISTER_TYPE_B;
141 case 16:
142 return BRW_REGISTER_TYPE_W;
143 case 32:
144 return BRW_REGISTER_TYPE_D;
145 case 64:
146 return BRW_REGISTER_TYPE_Q;
147 default:
148 unreachable("Invalid bit size");
149 }
150 case BRW_REGISTER_TYPE_UB:
151 case BRW_REGISTER_TYPE_UW:
152 case BRW_REGISTER_TYPE_UD:
153 case BRW_REGISTER_TYPE_UQ:
154 switch(bit_size) {
155 case 8:
156 return BRW_REGISTER_TYPE_UB;
157 case 16:
158 return BRW_REGISTER_TYPE_UW;
159 case 32:
160 return BRW_REGISTER_TYPE_UD;
161 case 64:
162 return BRW_REGISTER_TYPE_UQ;
163 default:
164 unreachable("Invalid bit size");
165 }
166 default:
167 unreachable("Unknown type");
168 }
169 }
170
171
172 #define INVALID_REG_TYPE ((enum brw_reg_type)-1)
173 #define INVALID_HW_REG_TYPE ((unsigned)-1)
174
175 unsigned
176 brw_reg_type_to_hw_type(const struct intel_device_info *devinfo,
177 enum brw_reg_file file, enum brw_reg_type type);
178
179 enum brw_reg_type ATTRIBUTE_PURE
180 brw_hw_type_to_reg_type(const struct intel_device_info *devinfo,
181 enum brw_reg_file file, unsigned hw_type);
182
183 unsigned
184 brw_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
185 enum brw_reg_type type);
186
187 unsigned
188 brw_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
189 enum brw_reg_type type);
190
191 enum brw_reg_type
192 brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
193 unsigned hw_type);
194
195 enum brw_reg_type
196 brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
197 unsigned hw_type, unsigned exec_type);
198
199 unsigned
200 brw_reg_type_to_size(enum brw_reg_type type);
201
202 const char *
203 brw_reg_type_to_letters(enum brw_reg_type type);
204
205 #ifdef __cplusplus
206 }
207 #endif
208
209 #endif
210