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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
H A Dbrw_fs_visitor.cpp163 this->pixel_x.type = BRW_REGISTER_TYPE_UW; in emit_interpolation_setup_gfx4()
164 this->pixel_y.type = BRW_REGISTER_TYPE_UW; in emit_interpolation_setup_gfx4()
351 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
355 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
361 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
365 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
369 int_pixel_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
374 half_int_pixel_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
375 half_int_pixel_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
421 fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
[all …]
/dports/lang/clover/mesa-21.3.6/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
H A Dbrw_fs_visitor.cpp163 this->pixel_x.type = BRW_REGISTER_TYPE_UW; in emit_interpolation_setup_gfx4()
164 this->pixel_y.type = BRW_REGISTER_TYPE_UW; in emit_interpolation_setup_gfx4()
351 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
355 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
361 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
365 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
369 int_pixel_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
374 half_int_pixel_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
375 half_int_pixel_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
421 fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
[all …]
/dports/graphics/libosmesa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
H A Dbrw_fs_visitor.cpp163 this->pixel_x.type = BRW_REGISTER_TYPE_UW; in emit_interpolation_setup_gfx4()
164 this->pixel_y.type = BRW_REGISTER_TYPE_UW; in emit_interpolation_setup_gfx4()
351 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
355 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
361 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
365 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
369 int_pixel_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
374 half_int_pixel_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
375 half_int_pixel_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
421 fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
[all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
H A Dbrw_fs_visitor.cpp163 this->pixel_x.type = BRW_REGISTER_TYPE_UW; in emit_interpolation_setup_gfx4()
164 this->pixel_y.type = BRW_REGISTER_TYPE_UW; in emit_interpolation_setup_gfx4()
351 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
355 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
361 int_pixel_offset_x = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
365 int_pixel_offset_y = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
369 int_pixel_offset_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
374 half_int_pixel_offset_x = bld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
375 half_int_pixel_offset_y = bld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
421 fs_reg int_pixel_xy = dbld.vgrf(BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gfx6()
[all …]
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
/dports/graphics/mesa-dri/mesa-21.3.6/src/intel/compiler/
H A Dbrw_reg_type.h61 BRW_REGISTER_TYPE_UW, /* 16-bit unsigned integer (word) */ enumerator
94 case BRW_REGISTER_TYPE_UW: in brw_reg_type_is_integer()
107 tp == BRW_REGISTER_TYPE_UW || in brw_reg_type_is_unsigned_integer()
151 case BRW_REGISTER_TYPE_UW: in brw_reg_type_from_bit_size()
158 return BRW_REGISTER_TYPE_UW; in brw_reg_type_from_bit_size()
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GFX11_HW_REG_TYPE_UW, GFX11_HW_IMM_TYPE_UW },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
296 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
311 [BRW_REGISTER_TYPE_UW] = { GFX12_HW_REG_TYPE_UINT(1), E(INT), },
519 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/compiler/
H A Dbrw_reg_type.c103 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
116 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
131 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
149 [BRW_REGISTER_TYPE_UW] = { BRW_HW_REG_TYPE_UW, BRW_HW_IMM_TYPE_UW },
165 [BRW_REGISTER_TYPE_UW] = { GEN11_HW_REG_TYPE_UW, GEN11_HW_IMM_TYPE_UW },
180 [BRW_REGISTER_TYPE_UW] = { GEN12_HW_REG_TYPE_UINT(1), GEN12_HW_REG_TYPE_UINT(1) },
253 [BRW_REGISTER_TYPE_UW] = { GEN10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
266 [BRW_REGISTER_TYPE_UW] = { GEN10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
278 [BRW_REGISTER_TYPE_UW] = { GEN12_HW_REG_TYPE_UINT(1), E(INT), },
476 [BRW_REGISTER_TYPE_UW] = 2, in brw_reg_type_to_size()
[all …]

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