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Searched refs:BRW_RT_SIZEOF_HIT_INFO (Results 1 – 21 of 21) sorted by relevance

/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/compiler/
H A Dbrw_rt.h165 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
179 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
184 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
188 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_lower_ray_queries.c206 BRW_RT_SIZEOF_HIT_INFO); in fill_query()
210 BRW_RT_SIZEOF_HIT_INFO); in fill_query()
231 BRW_RT_SIZEOF_HIT_INFO); in spill_query()
239 BRW_RT_SIZEOF_HIT_INFO); in spill_query()
360 BRW_RT_SIZEOF_HIT_INFO); in lower_ray_query_intrinsic()
H A Dbrw_nir_rt_builder.h238 return nir_iadd_imm(b, stack_addr, committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr_from_addr()
245 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
268 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
544 for (unsigned offset = 0; offset < BRW_RT_SIZEOF_HIT_INFO; offset += 16) { in brw_nir_rt_commit_hit_addr()
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_rt.h162 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
176 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
181 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_rt_builder.h143 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
165 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
328 BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_commit_hit()
/dports/lang/clover/mesa-21.3.6/src/intel/compiler/
H A Dbrw_rt.h162 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
176 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
181 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_rt_builder.h143 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
165 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
328 BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_commit_hit()
/dports/graphics/libosmesa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_rt.h162 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
176 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
181 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_rt_builder.h143 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
165 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
328 BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_commit_hit()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/compiler/
H A Dbrw_rt.h162 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
176 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
181 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_rt_builder.h143 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
165 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
328 BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_commit_hit()
/dports/graphics/mesa-libs/mesa-21.3.6/src/intel/compiler/
H A Dbrw_rt.h162 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
176 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
181 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_rt_builder.h143 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
165 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
328 BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_commit_hit()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/compiler/
H A Dbrw_rt.h162 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
176 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
181 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_rt_builder.h143 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
165 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
328 BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_commit_hit()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/compiler/
H A Dbrw_rt.h162 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
176 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
181 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_rt_builder.h143 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
165 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
328 BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_commit_hit()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/compiler/
H A Dbrw_rt.h162 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
176 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
181 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_rt_builder.h143 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
165 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
328 BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_commit_hit()
/dports/graphics/mesa-dri/mesa-21.3.6/src/intel/compiler/
H A Dbrw_rt.h162 #define BRW_RT_SIZEOF_HIT_INFO 32 macro
176 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
181 (BRW_RT_SIZEOF_HIT_INFO * 2 + \
H A Dbrw_nir_rt_builder.h143 committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_mem_hit_addr()
165 uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + in brw_nir_rt_mem_ray_addr()
328 BRW_RT_SIZEOF_HIT_INFO); in brw_nir_rt_commit_hit()