BUILD_VECTOR (reference) in projects: dports

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched refs:BUILD_VECTOR (Results 1 – 25 of 2948) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...118

/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fsqrt.mir	97 ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) 104 ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) 111 ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) 130 ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) 138 ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) 200 ; SI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) 207 ; VI: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) 214 ; GFX9: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) 297 ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<4 x s16>) 306 ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<4 x s16>) [all …]
H A D	legalize-build-vector.mir	13 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>) 29 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>) 47 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>) 67 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<5 x s32>) 89 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<6 x s32>) 113 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<7 x s32>) 139 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<8 x s32>) 167 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<9 x s32>) 197 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<10 x s32>) 613 ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x p3>) [all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 13 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 32 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32) 33 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 54 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 77 …; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]… 120 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 121 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 140 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32) 141 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) [all …]
H A D	legalize-build-vector.mir	14 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[C… 15 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 33 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64) 34 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>) 50 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0) 51 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x p0>) 66 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]]… 67 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<16 x s8>) 82 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]](… 83 ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<8 x s8>)
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 13 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 32 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32) 33 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 54 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 77 …; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]… 120 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 121 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 140 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32) 141 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) [all …]
H A D	legalize-build-vector.mir	14 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[C… 15 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 33 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64) 34 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>) 50 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0) 51 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x p0>) 66 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]]… 67 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<16 x s8>) 82 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]](… 83 ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<8 x s8>)
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 13 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 32 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32) 33 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 54 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 77 …; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]… 120 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 121 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 140 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32) 141 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) [all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 13 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 32 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32) 33 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 54 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 77 …; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]… 120 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 121 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 140 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32) 141 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) [all …]
H A D	legalize-build-vector.mir	14 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[C… 15 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 33 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64) 34 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>) 50 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0) 51 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x p0>) 66 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]]… 67 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<16 x s8>) 82 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]](… 83 ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<8 x s8>)
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 13 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 32 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32) 33 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 54 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 77 …; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]… 120 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 121 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 140 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32) 141 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) [all …]
H A D	legalize-build-vector.mir	14 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[C… 15 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 33 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64) 34 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>) 50 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0) 51 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x p0>) 66 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]]… 67 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<16 x s8>) 82 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]](… 83 ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<8 x s8>)
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 13 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 32 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32) 33 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 54 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 77 …; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]… 120 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 121 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 140 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32) 141 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 13 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 32 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32) 33 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 54 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 77 …; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]… 120 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 121 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 140 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32) 141 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) [all …]
H A D	legalize-build-vector.mir	14 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[C… 15 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 33 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64) 34 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>) 50 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0) 51 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x p0>) 66 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]]… 67 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<16 x s8>) 82 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]](… 83 ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<8 x s8>)
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 13 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 32 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32) 33 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 54 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 77 …; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]… 120 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 121 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 140 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32) 141 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) [all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	12 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 13 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 32 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY]](s32) 33 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 54 ; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>) 77 …; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[C]… 120 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 121 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) 140 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY]](s32) 141 ; CHECK: $x0 = COPY [[BUILD_VECTOR]](<2 x s32>) [all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	regbankselect-build-vector.mir	15 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 32 … ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 85 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 107 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 129 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 152 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 175 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 197 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>) 221 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>) 250 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>) [all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	regbankselect-build-vector.mir	15 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 32 … ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 85 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 107 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 129 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 152 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 175 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 197 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>) 221 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>) 250 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>) [all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/
H A D	regbankselect-build-vector.mir	15 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 32 … ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 85 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 107 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 129 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 152 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 175 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 197 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>) 221 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>) 250 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>) [all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	regbankselect-build-vector.mir	15 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 32 … ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 85 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 107 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 129 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 152 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 175 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 197 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>) 221 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>) 250 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>) [all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	regbankselect-build-vector.mir	15 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 32 … ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 85 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 107 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 129 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 152 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 175 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 197 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>) 221 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>) 250 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>) [all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	regbankselect-build-vector.mir	15 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 32 … ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 85 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 107 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 129 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 152 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 175 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 197 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>) 221 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>) 250 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>) [all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	regbankselect-build-vector.mir	15 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 32 … ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 85 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 107 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 129 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 152 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 175 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 197 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>) 221 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>) 250 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>) [all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	regbankselect-build-vector.mir	15 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 32 … ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 85 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 107 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 129 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 152 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 175 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 197 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>) 221 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>) 250 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>) [all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	regbankselect-build-vector.mir	15 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32) 32 … ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32) 85 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 107 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 129 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 152 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 175 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>) 197 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>) 221 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>) 250 ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>) [all …]

12 3 4 5 6 7 8 9 10 >>...118