1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
3# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
4
5---
6name: build_vector_v2s32_ss
7legalized: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0, $sgpr1
12    ; CHECK-LABEL: name: build_vector_v2s32_ss
13    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
14    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
15    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
16    %0:_(s32) = COPY $sgpr0
17    %1:_(s32) = COPY $sgpr1
18    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
19...
20
21---
22name: build_vector_v2s32_sv
23legalized: true
24
25body: |
26  bb.0:
27    liveins: $sgpr0, $vgpr0
28    ; CHECK-LABEL: name: build_vector_v2s32_sv
29    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
30    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
31    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
32    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
33    %0:_(s32) = COPY $sgpr0
34    %1:_(s32) = COPY $vgpr0
35    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
36...
37
38---
39name: build_vector_v2s32_vs
40legalized: true
41
42body: |
43  bb.0:
44    liveins: $vgpr0, $sgpr0
45    ; CHECK-LABEL: name: build_vector_v2s32_vs
46    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
47    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
48    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
49    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY2]](s32)
50    %0:_(s32) = COPY $vgpr0
51    %1:_(s32) = COPY $sgpr0
52    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
53...
54
55---
56name: build_vector_v2s32_vv
57legalized: true
58
59body: |
60  bb.0:
61    liveins: $vgpr0, $vgpr1
62    ; CHECK-LABEL: name: build_vector_v2s32_vv
63    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
64    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
65    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
66    %0:_(s32) = COPY $vgpr0
67    %1:_(s32) = COPY $vgpr1
68    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
69...
70
71---
72name: build_vector_v2s32_aa
73tracksRegLiveness: true
74legalized: true
75
76body: |
77  bb.0:
78    liveins: $agpr0, $agpr1
79
80    ; CHECK-LABEL: name: build_vector_v2s32_aa
81    ; CHECK: liveins: $agpr0, $agpr1
82    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
83    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
84    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
85    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
86    %0:_(s32) = COPY $agpr0
87    %1:_(s32) = COPY $agpr1
88    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
89    S_ENDPGM 0, implicit %2
90...
91
92---
93name: build_vector_v2s32_va
94tracksRegLiveness: true
95legalized: true
96
97body: |
98  bb.0:
99    liveins: $vgpr0, $agpr0
100
101    ; CHECK-LABEL: name: build_vector_v2s32_va
102    ; CHECK: liveins: $vgpr0, $agpr0
103    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
104    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
105    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
106    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY2]](s32)
107    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
108    %0:_(s32) = COPY $vgpr0
109    %1:_(s32) = COPY $agpr0
110    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
111    S_ENDPGM 0, implicit %2
112...
113
114---
115name: build_vector_v2s32_av
116tracksRegLiveness: true
117legalized: true
118
119body: |
120  bb.0:
121    liveins: $vgpr0, $agpr0
122
123    ; CHECK-LABEL: name: build_vector_v2s32_av
124    ; CHECK: liveins: $vgpr0, $agpr0
125    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
126    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
127    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
128    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
129    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
130    %0:_(s32) = COPY $agpr0
131    %1:_(s32) = COPY $vgpr0
132    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
133    S_ENDPGM 0, implicit %2
134...
135
136---
137name: build_vector_v2s32_sa
138tracksRegLiveness: true
139legalized: true
140
141body: |
142  bb.0:
143    liveins: $sgpr0, $agpr0
144
145    ; CHECK-LABEL: name: build_vector_v2s32_sa
146    ; CHECK: liveins: $sgpr0, $agpr0
147    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
148    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
149    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
150    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
151    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
152    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
153    %0:_(s32) = COPY $sgpr0
154    %1:_(s32) = COPY $agpr0
155    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
156    S_ENDPGM 0, implicit %2
157...
158
159---
160name: build_vector_v2s32_as
161tracksRegLiveness: true
162legalized: true
163
164body: |
165  bb.0:
166    liveins: $sgpr0, $agpr0
167
168    ; CHECK-LABEL: name: build_vector_v2s32_as
169    ; CHECK: liveins: $sgpr0, $agpr0
170    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
171    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
172    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
173    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
174    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
175    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
176    %0:_(s32) = COPY $agpr0
177    %1:_(s32) = COPY $sgpr0
178    %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
179    S_ENDPGM 0, implicit %2
180...
181
182---
183name: build_vector_v3s32_aaa
184tracksRegLiveness: true
185legalized: true
186
187body: |
188  bb.0:
189    liveins: $agpr0, $agpr1, $agpr2
190
191    ; CHECK-LABEL: name: build_vector_v3s32_aaa
192    ; CHECK: liveins: $agpr0, $agpr1, $agpr2
193    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
194    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
195    ; CHECK: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
196    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
197    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>)
198    %0:_(s32) = COPY $agpr0
199    %1:_(s32) = COPY $agpr1
200    %2:_(s32) = COPY $agpr2
201    %3:_(<3 x s32>) = G_BUILD_VECTOR %0, %1, %2
202    S_ENDPGM 0, implicit %3
203...
204
205---
206name: build_vector_v4s32_aaaa
207tracksRegLiveness: true
208legalized: true
209
210body: |
211  bb.0:
212    liveins: $agpr0, $agpr1, $agpr2
213
214    ; CHECK-LABEL: name: build_vector_v4s32_aaaa
215    ; CHECK: liveins: $agpr0, $agpr1, $agpr2
216    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
217    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
218    ; CHECK: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
219    ; CHECK: [[COPY3:%[0-9]+]]:agpr(s32) = COPY $agpr2
220    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
221    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<4 x s32>)
222    %0:_(s32) = COPY $agpr0
223    %1:_(s32) = COPY $agpr1
224    %2:_(s32) = COPY $agpr2
225    %3:_(s32) = COPY $agpr2
226    %4:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3
227    S_ENDPGM 0, implicit %4
228...
229
230---
231name: build_vector_v8s32_aaaaaaaa
232tracksRegLiveness: true
233legalized: true
234
235body: |
236  bb.0:
237    liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7
238
239    ; CHECK-LABEL: name: build_vector_v8s32_aaaaaaaa
240    ; CHECK: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7
241    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
242    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
243    ; CHECK: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
244    ; CHECK: [[COPY3:%[0-9]+]]:agpr(s32) = COPY $agpr3
245    ; CHECK: [[COPY4:%[0-9]+]]:agpr(s32) = COPY $agpr4
246    ; CHECK: [[COPY5:%[0-9]+]]:agpr(s32) = COPY $agpr5
247    ; CHECK: [[COPY6:%[0-9]+]]:agpr(s32) = COPY $agpr6
248    ; CHECK: [[COPY7:%[0-9]+]]:agpr(s32) = COPY $agpr7
249    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
250    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<8 x s32>)
251    %0:_(s32) = COPY $agpr0
252    %1:_(s32) = COPY $agpr1
253    %2:_(s32) = COPY $agpr2
254    %3:_(s32) = COPY $agpr3
255    %4:_(s32) = COPY $agpr4
256    %5:_(s32) = COPY $agpr5
257    %6:_(s32) = COPY $agpr6
258    %7:_(s32) = COPY $agpr7
259    %8:_(<8 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7
260    S_ENDPGM 0, implicit %8
261...
262
263---
264name: build_vector_v16s32_aaaaaaaaaaaaaaaa
265tracksRegLiveness: true
266legalized: true
267
268body: |
269  bb.0:
270    liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15
271
272    ; CHECK-LABEL: name: build_vector_v16s32_aaaaaaaaaaaaaaaa
273    ; CHECK: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4, $agpr5, $agpr6, $agpr7, $agpr8, $agpr9, $agpr10, $agpr11, $agpr12, $agpr13, $agpr14, $agpr15
274    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
275    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
276    ; CHECK: [[COPY2:%[0-9]+]]:agpr(s32) = COPY $agpr2
277    ; CHECK: [[COPY3:%[0-9]+]]:agpr(s32) = COPY $agpr3
278    ; CHECK: [[COPY4:%[0-9]+]]:agpr(s32) = COPY $agpr4
279    ; CHECK: [[COPY5:%[0-9]+]]:agpr(s32) = COPY $agpr5
280    ; CHECK: [[COPY6:%[0-9]+]]:agpr(s32) = COPY $agpr6
281    ; CHECK: [[COPY7:%[0-9]+]]:agpr(s32) = COPY $agpr7
282    ; CHECK: [[COPY8:%[0-9]+]]:agpr(s32) = COPY $agpr8
283    ; CHECK: [[COPY9:%[0-9]+]]:agpr(s32) = COPY $agpr9
284    ; CHECK: [[COPY10:%[0-9]+]]:agpr(s32) = COPY $agpr10
285    ; CHECK: [[COPY11:%[0-9]+]]:agpr(s32) = COPY $agpr11
286    ; CHECK: [[COPY12:%[0-9]+]]:agpr(s32) = COPY $agpr12
287    ; CHECK: [[COPY13:%[0-9]+]]:agpr(s32) = COPY $agpr13
288    ; CHECK: [[COPY14:%[0-9]+]]:agpr(s32) = COPY $agpr14
289    ; CHECK: [[COPY15:%[0-9]+]]:agpr(s32) = COPY $agpr15
290    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<16 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
291    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<16 x s32>)
292    %0:_(s32) = COPY $agpr0
293    %1:_(s32) = COPY $agpr1
294    %2:_(s32) = COPY $agpr2
295    %3:_(s32) = COPY $agpr3
296    %4:_(s32) = COPY $agpr4
297    %5:_(s32) = COPY $agpr5
298    %6:_(s32) = COPY $agpr6
299    %7:_(s32) = COPY $agpr7
300    %8:_(s32) = COPY $agpr8
301    %9:_(s32) = COPY $agpr9
302    %10:_(s32) = COPY $agpr10
303    %11:_(s32) = COPY $agpr11
304    %12:_(s32) = COPY $agpr12
305    %13:_(s32) = COPY $agpr13
306    %14:_(s32) = COPY $agpr14
307    %15:_(s32) = COPY $agpr15
308    %16:_(<16 x s32>) = G_BUILD_VECTOR %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14, %15
309    S_ENDPGM 0, implicit %16
310...
311