Searched refs:CLK90 (Results 1 – 16 of 16) sorted by relevance
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/gatemate/ |
| H A D | cells_bb.v | 32 output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT port
44 output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/models/ |
| H A D | DCM_SP.v | 33 CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90,
63 output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; port
67 reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; register
584 CLK90 = 0;
1020 assign CLK90 = 0;
1031 deassign CLK90;
1043 CLK90 <= #(clkout_delay + period / 4) clk0_out && !dll_mode_type && (clkfb_type != 2'b00);
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| /dports/cad/digital/Digital-0.27/src/main/resources/verilog/ |
| H A D | DIG_DCM_SP.v | 43 .CLK90(), // 1-bit output: 90 degree clock output
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| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-sha256crypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 112 .CLK90 (dcm0_clk90),
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| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-sha512crypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 112 .CLK90 (dcm0_clk90),
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| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-md5crypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 112 .CLK90 (dcm0_clk90),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/ |
| H A D | b200_clk_gen.v | 121 .CLK90 (),
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| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-bcrypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 107 .CLK90 (dcm0_clk90),
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| H A D | cmt_common.v | 62 .CLK90 (dcm0_clk90),
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| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-descrypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 108 .CLK90 (dcm0_clk90),
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| H A D | cmt_common.v | 62 .CLK90 (dcm0_clk90),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/top/N2x0/ |
| H A D | u2plus.v | 217 .CLK90(),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/top/USRP2/ |
| H A D | u2_rev3.v | 254 .CLK90(clk90),
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| /dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/ |
| H A D | cells_xtra.v | 7530 output CLK90; port
7567 output CLK90; port
7621 output CLK90; port
7664 output CLK90; port
7696 output CLK90; port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/planahead/planahead.runs/impl_1/ |
| H A D | b200.edf | 330 (port CLK90 (direction OUTPUT))
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/planahead/planahead.data/cache/ |
| H A D | b200_ngc_d1c0f267.edif | 169 (port CLK90
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