| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | cpu.h | 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 macro
48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 macro
|