1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017-2018, 2020 NXP 4 * Copyright 2014-2015, Freescale Semiconductor 5 */ 6 7 #ifndef _FSL_LAYERSCAPE_CPU_H 8 #define _FSL_LAYERSCAPE_CPU_H 9 10 #ifdef CONFIG_FSL_LSCH3 11 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 12 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 13 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 14 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 15 #ifndef CONFIG_NXP_LSCH3_2 16 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 17 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 18 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 19 #endif 20 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 21 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 22 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 23 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 24 #ifndef CONFIG_NXP_LSCH3_2 25 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 26 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 27 #endif 28 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 29 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 30 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 31 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000 32 #define CONFIG_SYS_FSL_NI_BASE 0x810000000 33 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000 34 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 35 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 36 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 37 #ifdef CONFIG_ARCH_LS2080A 38 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 39 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 40 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 41 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 42 #else 43 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 44 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 45 #ifndef CONFIG_SYS_PCIE3_PHYS_SIZE 46 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 47 #endif 48 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 49 #define SYS_PCIE5_PHYS_SIZE 0x800000000 50 #define SYS_PCIE6_PHYS_SIZE 0x800000000 51 #endif 52 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 53 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 54 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 55 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 56 #if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162) 57 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 58 #else 59 #define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000 60 #endif 61 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 62 #ifdef CONFIG_NXP_LSCH3_2 63 #define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 64 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 65 #define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 66 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 67 #else 68 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 69 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 70 #endif 71 #elif defined(CONFIG_FSL_LSCH2) 72 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 73 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 74 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 75 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 76 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 77 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 78 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000 79 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 80 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 81 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 82 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 83 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 84 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 85 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ 86 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 87 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 88 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 89 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 90 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ 91 #endif 92 93 int fsl_qoriq_core_to_cluster(unsigned int core); 94 u32 cpu_mask(void); 95 96 #endif /* _FSL_LAYERSCAPE_CPU_H */ 97