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Searched refs:CP0C5_MI (Results 1 – 25 of 34) sorted by relevance

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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/tcg/sysemu/
H A Dtlb_helper.c85 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
115 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
171 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
234 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
396 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
1368 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
H A Dcp0_helper.c1342 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1399 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
/dports/emulators/qemu/qemu-6.2.0/target/mips/tcg/sysemu/
H A Dtlb_helper.c85 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbinv()
115 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbwi()
171 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbp()
234 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbr()
396 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_map_address()
1368 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_invalidate_tlb()
H A Dcp0_helper.c1342 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1399 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dop_helper.c658 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbinv()
688 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbwi()
744 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbp()
807 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbr()
H A Dtlb_helper.c75 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_map_address()
1287 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_invalidate_tlb()
H A Dcpu.h942 #define CP0C5_MI 17 macro
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dop_helper.c661 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbinv()
691 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbwi()
747 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbp()
810 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbr()
H A Dhelper.c76 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_map_address()
1428 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_invalidate_tlb()
H A Dcpu.h929 #define CP0C5_MI 17 macro
H A Dcp0_helper.c1344 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1401 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dop_helper.c661 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbinv()
691 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbwi()
747 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbp()
810 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbr()
H A Dhelper.c76 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_map_address()
1428 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_invalidate_tlb()
H A Dcpu.h927 #define CP0C5_MI 17 macro
H A Dcp0_helper.c1311 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1368 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dcpu.h486 #define CP0C5_MI 17 macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dhelper.c86 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
1656 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
H A Dop_helper.c742 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbinv()
772 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
861 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
924 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1);
H A Dcp0_helper.c1342 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1399 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dcpu.h927 #define CP0C5_MI 17 macro
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dcpu.h927 #define CP0C5_MI 17 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dcpu.c295 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
H A Dcpu.h942 #define CP0C5_MI 17
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dcpu.c295 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in mips_cpu_reset()
H A Dcpu.h942 #define CP0C5_MI 17 macro

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