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Searched refs:CP0TCSt_TMX (Results 1 – 25 of 42) sorted by relevance

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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/sysemu/
H A Dcp0.c36 | (1 << CP0TCSt_TMX) in sync_c0_status()
46 tcstatus |= mx << CP0TCSt_TMX; in sync_c0_status()
/dports/emulators/qemu/qemu-6.2.0/target/mips/sysemu/
H A Dcp0.c36 | (1 << CP0TCSt_TMX) in sync_c0_status()
46 tcstatus |= mx << CP0TCSt_TMX; in sync_c0_status()
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dcpu.c50 | (1 << CP0TCSt_TMX) in sync_c0_status()
60 tcstatus |= mx << CP0TCSt_TMX; in sync_c0_status()
H A Dcpu.h480 #define CP0TCSt_TMX 27 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/mips/
H A Dhelper.c355 | (1 << CP0TCSt_TMX) in sync_c0_status()
365 tcstatus |= mx << CP0TCSt_TMX; in sync_c0_status()
H A Dcpu.h139 #define CP0TCSt_TMX 27 macro
H A Dtranslate_init.inc.c271 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c370 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
H A Dcpu.h181 #define CP0TCSt_TMX 27
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-mips/
H A Dtranslate_init.c370 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
H A Dcpu.h181 #define CP0TCSt_TMX 27 macro
/dports/emulators/qemu-utils/qemu-4.2.1/target/mips/
H A Dhelper.c365 | (1 << CP0TCSt_TMX) in sync_c0_status()
375 tcstatus |= mx << CP0TCSt_TMX; in sync_c0_status()
H A Dcpu.h472 #define CP0TCSt_TMX 27 macro
H A Dtranslate_init.inc.c271 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
/dports/emulators/qemu5/qemu-5.2.0/target/mips/
H A Dhelper.c371 | (1 << CP0TCSt_TMX) in sync_c0_status()
381 tcstatus |= mx << CP0TCSt_TMX; in sync_c0_status()
H A Dcpu.h473 #define CP0TCSt_TMX 27 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/mips/
H A Dhelper.c371 | (1 << CP0TCSt_TMX) in sync_c0_status()
381 tcstatus |= mx << CP0TCSt_TMX; in sync_c0_status()
H A Dcpu.h472 #define CP0TCSt_TMX 27 macro
H A Dtranslate_init.inc.c271 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
/dports/emulators/qemu42/qemu-4.2.1/target/mips/
H A Dhelper.c365 | (1 << CP0TCSt_TMX) in sync_c0_status()
375 tcstatus |= mx << CP0TCSt_TMX; in sync_c0_status()
H A Dcpu.h472 #define CP0TCSt_TMX 27 macro
H A Dtranslate_init.inc.c271 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/mips/
H A Dhelper.c447 | (1 << CP0TCSt_TMX)
457 tcstatus |= mx << CP0TCSt_TMX;
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/
H A Dcpu.h480 #define CP0TCSt_TMX 27
/dports/emulators/qemu/qemu-6.2.0/target/mips/
H A Dcpu.h480 #define CP0TCSt_TMX 27 macro

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