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Searched refs:CPSR_GE (Results 1 – 25 of 47) sorted by relevance

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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/
H A Dcpu.h242 #define CPSR_GE (0xf << 16) macro
254 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
256 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dunicorn_arm.c72 … *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & (CPSR_NZCV | CPSR_Q | CPSR_GE); in arm_reg_read()
138 … cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, (CPSR_NZCV | CPSR_Q | CPSR_GE)); in arm_reg_write()
H A Dcpu.h442 #define CPSR_GE (0xfU << 16) macro
461 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
464 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dunicorn_arm.c72 … *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & (CPSR_NZCV | CPSR_Q | CPSR_GE); in arm_reg_read()
138 … cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value, (CPSR_NZCV | CPSR_Q | CPSR_GE)); in arm_reg_write()
H A Dcpu.h442 #define CPSR_GE (0xfU << 16) macro
461 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
464 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dcpu.h1035 #define CPSR_GE (0xfU << 16) macro
1054 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1057 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1067 #define XPSR_GE CPSR_GE
H A Dmachine.c492 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); in get_cpsr()
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dcpu.h1149 #define CPSR_GE (0xfU << 16) macro
1168 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1171 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1181 #define XPSR_GE CPSR_GE
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dcpu.h1149 #define CPSR_GE (0xfU << 16) macro
1168 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1171 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1181 #define XPSR_GE CPSR_GE
H A Dmachine.c541 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); in get_cpsr()
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dcpu.h1234 #define CPSR_GE (0xfU << 16) macro
1248 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1251 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1259 #define XPSR_GE CPSR_GE
H A Dinternals.h1178 valid |= CPSR_E | CPSR_GE; in aarch32_cpsr_valid_mask()
H A Dmachine.c542 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); in get_cpsr()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dcpu.h1202 #define CPSR_GE (0xfU << 16) macro
1216 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1219 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1227 #define XPSR_GE CPSR_GE
H A Dinternals.h1137 valid |= CPSR_E | CPSR_GE; in aarch32_cpsr_valid_mask()
H A Dmachine.c542 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); in get_cpsr()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dcpu.h1202 #define CPSR_GE (0xfU << 16) macro
1216 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1219 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1227 #define XPSR_GE CPSR_GE
H A Dinternals.h1137 valid |= CPSR_E | CPSR_GE; in aarch32_cpsr_valid_mask()
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dcpu.h1250 #define CPSR_GE (0xfU << 16) macro
1266 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1269 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1277 #define XPSR_GE CPSR_GE
H A Dinternals.h976 valid |= CPSR_E | CPSR_GE; in aarch32_cpsr_valid_mask()
H A Dmachine.c542 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); in get_cpsr()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dcpu.h1262 #define CPSR_GE (0xfU << 16) macro
1278 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1281 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1289 #define XPSR_GE CPSR_GE
H A Dinternals.h990 valid |= CPSR_E | CPSR_GE; in aarch32_cpsr_valid_mask()
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dcpu.h1262 #define CPSR_GE (0xfU << 16) macro
1278 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1281 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1289 #define XPSR_GE CPSR_GE
H A Dinternals.h998 valid |= CPSR_E | CPSR_GE; in aarch32_cpsr_valid_mask()

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