/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/ |
H A D | cpu.h | 253 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 254 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) 258 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
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/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu.h | 460 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 461 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 466 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu.h | 460 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 461 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 466 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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/dports/emulators/qemu/qemu-6.2.0/linux-user/arm/ |
H A D | signal.c | 193 cpsr &= ~CPSR_IT; in setup_return() 232 cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
H A D | cpu.h | 1053 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 1054 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1059 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1077 #define XPSR_IT CPSR_IT
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H A D | machine.c | 492 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); in get_cpsr()
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/dports/emulators/qemu42/qemu-4.2.1/linux-user/arm/ |
H A D | signal.c | 241 cpsr &= ~CPSR_IT; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu60/qemu-6.0.0/linux-user/arm/ |
H A D | signal.c | 237 cpsr &= ~CPSR_IT; in setup_return() 291 cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-utils/qemu-4.2.1/linux-user/arm/ |
H A D | signal.c | 241 cpsr &= ~CPSR_IT; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/linux-user/arm/ |
H A D | signal.c | 241 cpsr &= ~CPSR_IT; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu5/qemu-5.2.0/linux-user/arm/ |
H A D | signal.c | 237 cpsr &= ~CPSR_IT; in setup_return() 291 cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/linux-user/arm/ |
H A D | signal.c | 241 cpsr &= ~CPSR_IT; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/linux-user/arm/ |
H A D | signal.c | 238 cpsr &= ~CPSR_IT; in setup_return() 292 cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/linux-user/arm/ |
H A D | signal.c | 241 cpsr &= ~CPSR_IT; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
H A D | cpu.h | 1167 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 1168 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1173 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1191 #define XPSR_IT CPSR_IT
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/dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
H A D | cpu.h | 1167 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 1168 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1173 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1191 #define XPSR_IT CPSR_IT
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/dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
H A D | cpu.h | 1247 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 1248 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1253 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1269 #define XPSR_IT CPSR_IT
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
H A D | cpu.h | 1215 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 1216 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1221 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1237 #define XPSR_IT CPSR_IT
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H A D | internals.h | 1140 valid |= CPSR_IT; in aarch32_cpsr_valid_mask()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
H A D | cpu.h | 1215 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 1216 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1221 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1237 #define XPSR_IT CPSR_IT
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/dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
H A D | cpu.h | 1265 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 1266 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1271 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1287 #define XPSR_IT CPSR_IT
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H A D | internals.h | 979 valid |= CPSR_IT; in aarch32_cpsr_valid_mask()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
H A D | cpu.h | 1277 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 1278 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1283 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1299 #define XPSR_IT CPSR_IT
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H A D | internals.h | 993 valid |= CPSR_IT; in aarch32_cpsr_valid_mask()
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/dports/emulators/qemu/qemu-6.2.0/target/arm/ |
H A D | cpu.h | 1277 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) macro 1278 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1283 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1299 #define XPSR_IT CPSR_IT
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