/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/ |
H A D | cpu.h | 235 #define CPSR_M (0x1f) macro 424 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; in cpu_mmu_index() 451 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) in cpu_get_tb_cpu_state()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
H A D | op_helper.c | 465 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 474 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER() 482 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 497 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()
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H A D | kvm32.c | 361 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_put_registers() 462 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_get_registers()
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H A D | arm-powerctl.c | 96 cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M, in arm_set_cpu_on_async_work()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
H A D | op_helper.c | 465 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 474 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER() 482 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 497 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()
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H A D | kvm32.c | 361 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_put_registers() 462 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_get_registers()
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/dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
H A D | op_helper.c | 468 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 477 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER() 485 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 500 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()
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H A D | arm-powerctl.c | 96 cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M, in arm_set_cpu_on_async_work()
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/dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
H A D | op_helper.c | 451 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 460 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER() 468 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 483 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()
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H A D | kvm32.c | 338 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_put_registers() 434 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_get_registers()
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H A D | arm-powerctl.c | 96 cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M, in arm_set_cpu_on_async_work()
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/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
H A D | op_helper.c | 451 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 460 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER() 468 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 483 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()
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H A D | kvm32.c | 338 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_put_registers() 434 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_get_registers()
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H A D | arm-powerctl.c | 96 cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M, in arm_set_cpu_on_async_work()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
H A D | op_helper.c | 486 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 495 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER() 503 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 518 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()
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H A D | arm-powerctl.c | 96 cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M, in arm_set_cpu_on_async_work()
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/dports/emulators/qemu/qemu-6.2.0/target/arm/ |
H A D | op_helper.c | 486 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 495 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER() 503 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 518 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()
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/dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
H A D | op_helper.c | 461 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 470 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER() 478 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 493 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks()
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H A D | arm-powerctl.c | 96 cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M, in arm_set_cpu_on_async_work()
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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/patches/ |
H A D | qemu-0.9.0-x49gp-arm-semihosting.patch | 42 - && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
H A D | op_helper.c | 599 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 608 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { in HELPER() 616 if ((env->uncached_cpsr & CPSR_M) == mode) { in HELPER() 631 int curmode = env->uncached_cpsr & CPSR_M; in msr_mrs_banked_exc_checks() 986 switch (spsr & CPSR_M) { in el_from_spsr()
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H A D | kvm32.c | 310 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_put_registers() 417 mode = env->uncached_cpsr & CPSR_M; in kvm_arch_get_registers()
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H A D | arm-powerctl.c | 96 cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M, in arm_set_cpu_on_async_work()
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/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu.h | 435 #define CPSR_M (0x1fU) macro 786 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_is_secure() 1499 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; in cpu_get_tb_cpu_state()
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/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu.h | 435 #define CPSR_M (0x1fU) macro 786 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { in arm_is_secure() 1499 privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; in cpu_get_tb_cpu_state()
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